Abstract
Time and energy is expended in switching between power modes (e.g., active, hibernate, sleep, etc.). Powering off cache is one major reason for this. When there is a switch in the power-mode involving cache power-off, the system spends time and energy in filling the cache with new data (inherent cache misses). In our technique, before powering off the cache, we save its state in Embedded DRAM and bring it back when the previous power mode is restored. Our experiments have showed that in a majority of cases the cache contents are too valuable to be erased. By saving the contents we can reduce switching speed and energy. We present a heuristic to save the most relevant cache contents so that power and delay overheads are minimized. To measure the area overhead a synthesizable VHDL model was designed.
Original language | English (US) |
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Pages (from-to) | 379-388 |
Number of pages | 10 |
Journal | International Journal of Software Engineering and Knowledge Engineering |
Volume | 15 |
Issue number | 2 |
DOIs | |
State | Published - Apr 2005 |
Keywords
- Architecture
- Cache
- EDRAM
- Power mode
- State
ASJC Scopus subject areas
- Software
- Computer Networks and Communications
- Computer Graphics and Computer-Aided Design
- Artificial Intelligence