Efficient prediction of 28nm path delay degradation under activity uncertainty

Devyani Patra; Ankita Bansal; Richard Rao; Anu Ramamurthy; Wencheng Li; Eskinder Shimelis; Yu Cao

doi:10.1109/IRPS.2017.7936354

Efficient prediction of 28nm path delay degradation under activity uncertainty

Devyani Patra, Ankita Bansal, Richard Rao, Anu Ramamurthy, Wencheng Li, Eskinder Shimelis, Yu Cao

Engineering, Ira A. Fulton Schools of (IAFSE)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Determining aging and End of Lifetime (EOL) for VLSI circuits can be a slow and cumbersome process. A simple extrapolation of aging results, under statistical variations and other uncertainties, may cause large errors in EOL prediction and over-margining. This work provides a fast and effective simulation solution to determine guard band against aging in a design. In this paper, we present an improved version of System Reliability Analyzer (SyRA), SyRA-X, to provide: (1) circuit aging calculation which is reliable under various switching activities at each node, (2) device, gate, and path level analysis of aging with dynamic inputs, and (3) verification of SyRA-X with a minimum guard band to give prediction over 99% accuracy.

Original language	English (US)
Title of host publication	2017 International Reliability Physics Symposium, IRPS 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	CR5.1-CR5.4
ISBN (Electronic)	9781509066407
DOIs	https://doi.org/10.1109/IRPS.2017.7936354
State	Published - May 30 2017
Event	2017 International Reliability Physics Symposium, IRPS 2017 - Monterey, United States Duration: Apr 2 2017 → Apr 6 2017

Other

Other	2017 International Reliability Physics Symposium, IRPS 2017
Country/Territory	United States
City	Monterey
Period	4/2/17 → 4/6/17

Keywords

Aging
Bias temperature instability
Circuit simulation
VLSI reliability

ASJC Scopus subject areas

General Engineering

Access to Document

10.1109/IRPS.2017.7936354

Cite this

Patra, D, Bansal, A, Rao, R, Ramamurthy, A, Li, W, Shimelis, E & Cao, Y 2017, Efficient prediction of 28nm path delay degradation under activity uncertainty. in 2017 International Reliability Physics Symposium, IRPS 2017., 7936354, Institute of Electrical and Electronics Engineers Inc., pp. CR5.1-CR5.4, 2017 International Reliability Physics Symposium, IRPS 2017, Monterey, United States, 4/2/17. https://doi.org/10.1109/IRPS.2017.7936354

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abstract = "Determining aging and End of Lifetime (EOL) for VLSI circuits can be a slow and cumbersome process. A simple extrapolation of aging results, under statistical variations and other uncertainties, may cause large errors in EOL prediction and over-margining. This work provides a fast and effective simulation solution to determine guard band against aging in a design. In this paper, we present an improved version of System Reliability Analyzer (SyRA), SyRA-X, to provide: (1) circuit aging calculation which is reliable under various switching activities at each node, (2) device, gate, and path level analysis of aging with dynamic inputs, and (3) verification of SyRA-X with a minimum guard band to give prediction over 99% accuracy.",

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author = "Devyani Patra and Ankita Bansal and Richard Rao and Anu Ramamurthy and Wencheng Li and Eskinder Shimelis and Yu Cao",

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AU - Rao, Richard

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AU - Li, Wencheng

AU - Shimelis, Eskinder

AU - Cao, Yu

PY - 2017/5/30

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N2 - Determining aging and End of Lifetime (EOL) for VLSI circuits can be a slow and cumbersome process. A simple extrapolation of aging results, under statistical variations and other uncertainties, may cause large errors in EOL prediction and over-margining. This work provides a fast and effective simulation solution to determine guard band against aging in a design. In this paper, we present an improved version of System Reliability Analyzer (SyRA), SyRA-X, to provide: (1) circuit aging calculation which is reliable under various switching activities at each node, (2) device, gate, and path level analysis of aging with dynamic inputs, and (3) verification of SyRA-X with a minimum guard band to give prediction over 99% accuracy.

AB - Determining aging and End of Lifetime (EOL) for VLSI circuits can be a slow and cumbersome process. A simple extrapolation of aging results, under statistical variations and other uncertainties, may cause large errors in EOL prediction and over-margining. This work provides a fast and effective simulation solution to determine guard band against aging in a design. In this paper, we present an improved version of System Reliability Analyzer (SyRA), SyRA-X, to provide: (1) circuit aging calculation which is reliable under various switching activities at each node, (2) device, gate, and path level analysis of aging with dynamic inputs, and (3) verification of SyRA-X with a minimum guard band to give prediction over 99% accuracy.

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Efficient prediction of 28nm path delay degradation under activity uncertainty

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Keywords

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