Efficient prediction of 28nm path delay degradation under activity uncertainty

Devyani Patra, Ankita Bansal, Richard Rao, Anu Ramamurthy, Wencheng Li, Eskinder Shimelis, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Determining aging and End of Lifetime (EOL) for VLSI circuits can be a slow and cumbersome process. A simple extrapolation of aging results, under statistical variations and other uncertainties, may cause large errors in EOL prediction and over-margining. This work provides a fast and effective simulation solution to determine guard band against aging in a design. In this paper, we present an improved version of System Reliability Analyzer (SyRA), SyRA-X, to provide: (1) circuit aging calculation which is reliable under various switching activities at each node, (2) device, gate, and path level analysis of aging with dynamic inputs, and (3) verification of SyRA-X with a minimum guard band to give prediction over 99% accuracy.

Original languageEnglish (US)
Title of host publication2017 International Reliability Physics Symposium, IRPS 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
PagesCR5.1-CR5.4
ISBN (Electronic)9781509066407
DOIs
StatePublished - May 30 2017
Event2017 International Reliability Physics Symposium, IRPS 2017 - Monterey, United States
Duration: Apr 2 2017Apr 6 2017

Other

Other2017 International Reliability Physics Symposium, IRPS 2017
CountryUnited States
CityMonterey
Period4/2/174/6/17

Keywords

  • Aging
  • Bias temperature instability
  • Circuit simulation
  • VLSI reliability

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Patra, D., Bansal, A., Rao, R., Ramamurthy, A., Li, W., Shimelis, E., & Cao, Y. (2017). Efficient prediction of 28nm path delay degradation under activity uncertainty. In 2017 International Reliability Physics Symposium, IRPS 2017 (pp. CR5.1-CR5.4). [7936354] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IRPS.2017.7936354