TY - JOUR
T1 - Efficient cache reconfiguration using machine learning in NoC-based many-core CMPs
AU - Charles, Subodha
AU - Ahmed, Alif
AU - Ogras, Umit Y.
AU - Mishra, Prabhat
N1 - Funding Information:
This work was partially supported by the NSF grants CNS-1526687 and CNS-1526562. Authors’ addresses: S. Charles, 320 University Village, Apt. 3, Gainesville, FL 32603; email: subodha96@ufl.edu; A. Ahmed, 137 Yellowstone Dr Apt 106, Charlottesville, VA 22903; email: alifahmed@ufl.edu; U. Ogras, 650 E Tyler Mall, Tempe, AZ 85287; email: umit@asu.edu; P. Mishra, 432 Newell Drive, Gainesville, FL 32611-6120; email: prabhat@ufl.edu. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from permissions@acm.org. © 2019 Association for Computing Machinery. 1084-4309/2019/09-ART60 $15.00 https://doi.org/10.1145/3350422
PY - 2019/11
Y1 - 2019/11
N2 - Dynamic cache reconfiguration (DCR) is an effective technique to optimize energy consumption inmany-core architectures. While early work on DCR has shown promising energy saving opportunities, prior techniques are not suitable for many-core architectures since they do not consider the interactions and tight coupling between memory, caches, and network-on-chip (NoC) traffic. In this article, we propose an efficient cache reconfiguration framework in NoC-based many-core architectures. The proposed work makes three major contributions. First, we model a distributed directory based many-core architecture similar to Intel Xeon Phi architecture. Next, we propose an efficient cache reconfiguration framework that considers all significant components, including NoC, caches, and main memory. Finally, we propose a machine learning-based framework that can reduce the exploration time by an order of magnitude with negligible loss in accuracy. Our experimental results demonstrate 18.5% energy savings on average compared to base cache configuration.
AB - Dynamic cache reconfiguration (DCR) is an effective technique to optimize energy consumption inmany-core architectures. While early work on DCR has shown promising energy saving opportunities, prior techniques are not suitable for many-core architectures since they do not consider the interactions and tight coupling between memory, caches, and network-on-chip (NoC) traffic. In this article, we propose an efficient cache reconfiguration framework in NoC-based many-core architectures. The proposed work makes three major contributions. First, we model a distributed directory based many-core architecture similar to Intel Xeon Phi architecture. Next, we propose an efficient cache reconfiguration framework that considers all significant components, including NoC, caches, and main memory. Finally, we propose a machine learning-based framework that can reduce the exploration time by an order of magnitude with negligible loss in accuracy. Our experimental results demonstrate 18.5% energy savings on average compared to base cache configuration.
KW - Cache reconfiguration
KW - Machine learning
UR - http://www.scopus.com/inward/record.url?scp=85075713282&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85075713282&partnerID=8YFLogxK
U2 - 10.1145/3350422
DO - 10.1145/3350422
M3 - Article
AN - SCOPUS:85075713282
VL - 24
JO - ACM Transactions on Design Automation of Electronic Systems
JF - ACM Transactions on Design Automation of Electronic Systems
SN - 1084-4309
IS - 6
M1 - 60
ER -