TY - GEN
T1 - Effects of global interconnect optimizations on performance estimation of deep submicron design
AU - Cao, Yu
AU - Hu, Chenming
AU - Huang, Xuejue
AU - Kahng, Andrew B.
AU - Muddu, Sudhakar
AU - Stroobandt, Dirk
AU - Sylvestel, Dennis
N1 - Publisher Copyright:
© 2000 IEEE.
PY - 2000
Y1 - 2000
N2 - In this paper, we quantify the impact of global interconnect optimization techniques that address such design objectives as delay, peak noise, delay uncertainty due to noise, power, and cost. In doing so, we develop a new system-performance simulation model as a set of studies within the MARCO GSRC Technology Extrapolation (GTX) system. We model a typical point-to-point global interconnect and focus on accurate assessment of both circuit and design technology with respect to such issues as inductance, signal line shielding, dynamic delay, buffer placement uncertainty and repeater staggering. We demonstrate, for example, that optimal wire sizing models need to consider inductive effects - And that use of more accurate (-1,3) worst-case capacitive coupling noise switch factors substantially increases peak noise estimates compared to traditional (0,2) bounds. We also find that optimal repeater sizes are significantly smaller than conventional models would suggest, especially when considering energy-delay issues.
AB - In this paper, we quantify the impact of global interconnect optimization techniques that address such design objectives as delay, peak noise, delay uncertainty due to noise, power, and cost. In doing so, we develop a new system-performance simulation model as a set of studies within the MARCO GSRC Technology Extrapolation (GTX) system. We model a typical point-to-point global interconnect and focus on accurate assessment of both circuit and design technology with respect to such issues as inductance, signal line shielding, dynamic delay, buffer placement uncertainty and repeater staggering. We demonstrate, for example, that optimal wire sizing models need to consider inductive effects - And that use of more accurate (-1,3) worst-case capacitive coupling noise switch factors substantially increases peak noise estimates compared to traditional (0,2) bounds. We also find that optimal repeater sizes are significantly smaller than conventional models would suggest, especially when considering energy-delay issues.
KW - Crosstalk noise
KW - Inductance
KW - Interconnect delay
KW - System performance models
KW - Technology extrapolation
KW - VLSI
UR - http://www.scopus.com/inward/record.url?scp=0034477838&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0034477838&partnerID=8YFLogxK
U2 - 10.1109/ICCAD.2000.896451
DO - 10.1109/ICCAD.2000.896451
M3 - Conference contribution
AN - SCOPUS:0034477838
T3 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
SP - 56
EP - 61
BT - IEEE/ACM International Conference on Computer Aided Design
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - IEEE/ACM International Conference on Computer Aided Design, ICCAD 2000
Y2 - 5 November 2000 through 9 November 2000
ER -