Dynamic voltage and frequency scaling for shared resources in multicore processor designs

Xi Chen; Zheng Xu; Hyungjun Kim; Paul V. Gratz; Jiang Hu; Michael Kishinevsky; Umit Ogras; Raid Ayoub

doi:10.1145/2463209.2488874

Dynamic voltage and frequency scaling for shared resources in multicore processor designs

Xi Chen, Zheng Xu, Hyungjun Kim, Paul V. Gratz, Jiang Hu, Michael Kishinevsky, Umit Ogras, Raid Ayoub

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

55 Scopus citations

Abstract

As the core count in processor chips grows, so do the on-die, shared resources such as on-chip communication fabric and shared cache, which are of paramount importance for chip performance and power. This paper presents a method for dynamic voltage/frequency scaling of networks-on-chip and last level caches in multicore processor designs, where the shared resources form a single voltage/frequency domain. Several new techniques for monitoring and control are de- veloped, and validated through full system simulations on the PARSEC benchmarks. These techniques reduce energy- delay product by 56% compared to a state-of-the-art prior work.

Original language	English (US)
Title of host publication	Proceedings of the 50th Annual Design Automation Conference, DAC 2013
DOIs	https://doi.org/10.1145/2463209.2488874
State	Published - Jul 12 2013
Externally published	Yes
Event	50th Annual Design Automation Conference, DAC 2013 - Austin, TX, United States Duration: May 29 2013 → Jun 7 2013

Publication series

Name	Proceedings - Design Automation Conference
ISSN (Print)	0738-100X

Other

Other	50th Annual Design Automation Conference, DAC 2013
Country/Territory	United States
City	Austin, TX
Period	5/29/13 → 6/7/13

ASJC Scopus subject areas

Computer Science Applications
Control and Systems Engineering
Electrical and Electronic Engineering
Modeling and Simulation

Access to Document

10.1145/2463209.2488874

Cite this

Chen, X, Xu, Z, Kim, H, Gratz, PV, Hu, J, Kishinevsky, M, Ogras, U & Ayoub, R 2013, Dynamic voltage and frequency scaling for shared resources in multicore processor designs. in Proceedings of the 50th Annual Design Automation Conference, DAC 2013., 114, Proceedings - Design Automation Conference, 50th Annual Design Automation Conference, DAC 2013, Austin, TX, United States, 5/29/13. https://doi.org/10.1145/2463209.2488874

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AU - Chen, Xi

AU - Xu, Zheng

AU - Kim, Hyungjun

AU - Gratz, Paul V.

AU - Hu, Jiang

AU - Kishinevsky, Michael

AU - Ogras, Umit

AU - Ayoub, Raid

PY - 2013/7/12

Y1 - 2013/7/12

N2 - As the core count in processor chips grows, so do the on-die, shared resources such as on-chip communication fabric and shared cache, which are of paramount importance for chip performance and power. This paper presents a method for dynamic voltage/frequency scaling of networks-on-chip and last level caches in multicore processor designs, where the shared resources form a single voltage/frequency domain. Several new techniques for monitoring and control are de- veloped, and validated through full system simulations on the PARSEC benchmarks. These techniques reduce energy- delay product by 56% compared to a state-of-the-art prior work.

AB - As the core count in processor chips grows, so do the on-die, shared resources such as on-chip communication fabric and shared cache, which are of paramount importance for chip performance and power. This paper presents a method for dynamic voltage/frequency scaling of networks-on-chip and last level caches in multicore processor designs, where the shared resources form a single voltage/frequency domain. Several new techniques for monitoring and control are de- veloped, and validated through full system simulations on the PARSEC benchmarks. These techniques reduce energy- delay product by 56% compared to a state-of-the-art prior work.

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M3 - Conference contribution

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Dynamic voltage and frequency scaling for shared resources in multicore processor designs

Abstract

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