Dynamic voltage and frequency scaling for shared resources in multicore processor designs

Xi Chen, Zheng Xu, Hyungjun Kim, Paul V. Gratz, Jiang Hu, Michael Kishinevsky, Umit Ogras, Raid Ayoub

Research output: Chapter in Book/Report/Conference proceedingConference contribution

46 Scopus citations

Abstract

As the core count in processor chips grows, so do the on-die, shared resources such as on-chip communication fabric and shared cache, which are of paramount importance for chip performance and power. This paper presents a method for dynamic voltage/frequency scaling of networks-on-chip and last level caches in multicore processor designs, where the shared resources form a single voltage/frequency domain. Several new techniques for monitoring and control are de- veloped, and validated through full system simulations on the PARSEC benchmarks. These techniques reduce energy- delay product by 56% compared to a state-of-the-art prior work.

Original languageEnglish (US)
Title of host publicationProceedings of the 50th Annual Design Automation Conference, DAC 2013
DOIs
StatePublished - Jul 12 2013
Externally publishedYes
Event50th Annual Design Automation Conference, DAC 2013 - Austin, TX, United States
Duration: May 29 2013Jun 7 2013

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Other

Other50th Annual Design Automation Conference, DAC 2013
CountryUnited States
CityAustin, TX
Period5/29/136/7/13

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation

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  • Cite this

    Chen, X., Xu, Z., Kim, H., Gratz, P. V., Hu, J., Kishinevsky, M., Ogras, U., & Ayoub, R. (2013). Dynamic voltage and frequency scaling for shared resources in multicore processor designs. In Proceedings of the 50th Annual Design Automation Conference, DAC 2013 [114] (Proceedings - Design Automation Conference). https://doi.org/10.1145/2463209.2488874