Digital built-in self-test for phased locked loops to enable fault detection

Mehmet Ince, Ender Yilmaz, Wei Fu, Joonsung Park, Krishnaswamy Nagaraj, Leroy Winemberg, Sule Ozev

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

With the increasing pressure to obtain near-zero defect rates for the automotive industry, there is a need to explore built-in self-test and other non-traditional test techniques for embedded mixed-signal components, such as PLLs, DC-DC converters, and data converters. This paper presents an extremely low-cost built-in self-test technique for PLLs specifically designed for fault detection. The methodology relies on exciting the PLL loop in one location via a pseudo-random signal with noise characteristics and observing the response from another location in the loop via all digital circuitry, thereby inducing low area and performance overhead. The BIST circuit along with a PLL under test is designed in 65nm technology. Fault simulations performed at the transistor and system level show that majority of non-catastrophic faults that result in parametric failures can be detected with the proposed approach.

Original languageEnglish (US)
Title of host publicationProceedings - 2019 IEEE European Test Symposium, ETS 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728111735
DOIs
StatePublished - May 1 2019
Event2019 IEEE European Test Symposium, ETS 2019 - Baden-Baden, Germany
Duration: May 27 2019May 31 2019

Publication series

NameProceedings of the European Test Workshop
Volume2019-May
ISSN (Print)1530-1877
ISSN (Electronic)1558-1780

Conference

Conference2019 IEEE European Test Symposium, ETS 2019
CountryGermany
CityBaden-Baden
Period5/27/195/31/19

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Industrial and Manufacturing Engineering
  • Software

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