Abstract
With the increasing pressure to obtain near-zero defect rates for the automotive industry, there is a need to explore built-in self-test and other non-traditional test techniques for embedded mixed-signal components, such as PLLs, DC-DC converters, and data converters. This paper presents an extremely low-cost built-in self-test technique for PLLs specifically designed for fault detection. The methodology relies on exciting the PLL loop in one location via a pseudo-random signal with noise characteristics and observing the response from another location in the loop via all digital circuitry, thereby inducing low area and performance overhead. The BIST circuit along with a PLL under test is designed in 65nm technology. Fault simulations performed at the transistor and system level show that majority of non-catastrophic faults that result in parametric failures can be detected with the proposed approach.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings - 2019 IEEE European Test Symposium, ETS 2019 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9781728111735 |
| DOIs | |
| State | Published - May 1 2019 |
| Event | 2019 IEEE European Test Symposium, ETS 2019 - Baden-Baden, Germany Duration: May 27 2019 → May 31 2019 |
Publication series
| Name | Proceedings of the European Test Workshop |
|---|---|
| Volume | 2019-May |
| ISSN (Print) | 1530-1877 |
| ISSN (Electronic) | 1558-1780 |
Conference
| Conference | 2019 IEEE European Test Symposium, ETS 2019 |
|---|---|
| Country | Germany |
| City | Baden-Baden |
| Period | 5/27/19 → 5/31/19 |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Industrial and Manufacturing Engineering
- Software
Cite this
Digital built-in self-test for phased locked loops to enable fault detection. / Ince, Mehmet; Yilmaz, Ender; Fu, Wei; Park, Joonsung; Nagaraj, Krishnaswamy; Winemberg, Leroy; Ozev, Sule.
Proceedings - 2019 IEEE European Test Symposium, ETS 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8791533 (Proceedings of the European Test Workshop; Vol. 2019-May).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Digital built-in self-test for phased locked loops to enable fault detection
AU - Ince, Mehmet
AU - Yilmaz, Ender
AU - Fu, Wei
AU - Park, Joonsung
AU - Nagaraj, Krishnaswamy
AU - Winemberg, Leroy
AU - Ozev, Sule
PY - 2019/5/1
Y1 - 2019/5/1
N2 - With the increasing pressure to obtain near-zero defect rates for the automotive industry, there is a need to explore built-in self-test and other non-traditional test techniques for embedded mixed-signal components, such as PLLs, DC-DC converters, and data converters. This paper presents an extremely low-cost built-in self-test technique for PLLs specifically designed for fault detection. The methodology relies on exciting the PLL loop in one location via a pseudo-random signal with noise characteristics and observing the response from another location in the loop via all digital circuitry, thereby inducing low area and performance overhead. The BIST circuit along with a PLL under test is designed in 65nm technology. Fault simulations performed at the transistor and system level show that majority of non-catastrophic faults that result in parametric failures can be detected with the proposed approach.
AB - With the increasing pressure to obtain near-zero defect rates for the automotive industry, there is a need to explore built-in self-test and other non-traditional test techniques for embedded mixed-signal components, such as PLLs, DC-DC converters, and data converters. This paper presents an extremely low-cost built-in self-test technique for PLLs specifically designed for fault detection. The methodology relies on exciting the PLL loop in one location via a pseudo-random signal with noise characteristics and observing the response from another location in the loop via all digital circuitry, thereby inducing low area and performance overhead. The BIST circuit along with a PLL under test is designed in 65nm technology. Fault simulations performed at the transistor and system level show that majority of non-catastrophic faults that result in parametric failures can be detected with the proposed approach.
UR - http://www.scopus.com/inward/record.url?scp=85071149934&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85071149934&partnerID=8YFLogxK
U2 - 10.1109/ETS.2019.8791533
DO - 10.1109/ETS.2019.8791533
M3 - Conference contribution
AN - SCOPUS:85071149934
T3 - Proceedings of the European Test Workshop
BT - Proceedings - 2019 IEEE European Test Symposium, ETS 2019
PB - Institute of Electrical and Electronics Engineers Inc.
ER -