Design rule optimization of regular layout for leakage reduction in nanoscale design

Anupama R. Subramaniam, Ritu Singhal, Chi Chao Wang, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations

Abstract

The effect of non-rectilinear gate (NRG) due to sub-wavelength lithograph dramatically increases the leakage current by more than 15X. To mitigate this penalty, we have developed a systematic procedure to optimize key layout parameters in regular layout with minimum area and speed overhead. As demonstrated in 65nm technology, the optimization of regular layout achieves more than 70% reduction in leakage under NRG, with area penalty of ∼10% and marginal impact on circuit speed and active power.

Original languageEnglish (US)
Title of host publication2008 Asia and South Pacific Design Automation Conference, ASP-DAC
Pages474-479
Number of pages6
DOIs
StatePublished - Aug 21 2008
Event2008 Asia and South Pacific Design Automation Conference, ASP-DAC - Seoul, Korea, Republic of
Duration: Mar 21 2008Mar 24 2008

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other2008 Asia and South Pacific Design Automation Conference, ASP-DAC
CountryKorea, Republic of
CitySeoul
Period3/21/083/24/08

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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    Subramaniam, A. R., Singhal, R., Wang, C. C., & Cao, Y. (2008). Design rule optimization of regular layout for leakage reduction in nanoscale design. In 2008 Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 474-479). [4483997] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2008.4483997