Design rule optimization of regular layout for leakage reduction in nanoscale design

Anupama R. Subramaniam; Ritu Singhal; Chi Chao Wang; Yu Cao

doi:10.1109/ASPDAC.2008.4483997

Design rule optimization of regular layout for leakage reduction in nanoscale design

Anupama R. Subramaniam, Ritu Singhal, Chi Chao Wang, Yu Cao

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

11 Scopus citations

Abstract

The effect of non-rectilinear gate (NRG) due to sub-wavelength lithograph dramatically increases the leakage current by more than 15X. To mitigate this penalty, we have developed a systematic procedure to optimize key layout parameters in regular layout with minimum area and speed overhead. As demonstrated in 65nm technology, the optimization of regular layout achieves more than 70% reduction in leakage under NRG, with area penalty of ∼10% and marginal impact on circuit speed and active power.

Original language	English (US)
Title of host publication	2008 Asia and South Pacific Design Automation Conference, ASP-DAC
Pages	474-479
Number of pages	6
DOIs	https://doi.org/10.1109/ASPDAC.2008.4483997
State	Published - 2008
Event	2008 Asia and South Pacific Design Automation Conference, ASP-DAC - Seoul, Korea, Republic of Duration: Mar 21 2008 → Mar 24 2008

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other	2008 Asia and South Pacific Design Automation Conference, ASP-DAC
Country/Territory	Korea, Republic of
City	Seoul
Period	3/21/08 → 3/24/08

ASJC Scopus subject areas

Computer Science Applications
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Access to Document

10.1109/ASPDAC.2008.4483997

Cite this

Subramaniam, A. R., Singhal, R., Wang, C. C., & Cao, Y. (2008). Design rule optimization of regular layout for leakage reduction in nanoscale design. In 2008 Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 474-479). Article 4483997 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2008.4483997

Design rule optimization of regular layout for leakage reduction in nanoscale design. / Subramaniam, Anupama R.; Singhal, Ritu; Wang, Chi Chao et al.
2008 Asia and South Pacific Design Automation Conference, ASP-DAC. 2008. p. 474-479 4483997 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Subramaniam, AR, Singhal, R, Wang, CC & Cao, Y 2008, Design rule optimization of regular layout for leakage reduction in nanoscale design. in 2008 Asia and South Pacific Design Automation Conference, ASP-DAC., 4483997, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 474-479, 2008 Asia and South Pacific Design Automation Conference, ASP-DAC, Seoul, Korea, Republic of, 3/21/08. https://doi.org/10.1109/ASPDAC.2008.4483997

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AB - The effect of non-rectilinear gate (NRG) due to sub-wavelength lithograph dramatically increases the leakage current by more than 15X. To mitigate this penalty, we have developed a systematic procedure to optimize key layout parameters in regular layout with minimum area and speed overhead. As demonstrated in 65nm technology, the optimization of regular layout achieves more than 70% reduction in leakage under NRG, with area penalty of ∼10% and marginal impact on circuit speed and active power.

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Design rule optimization of regular layout for leakage reduction in nanoscale design

Abstract

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ASJC Scopus subject areas

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