Design guidelines for 3D RRAM cross-point architecture

Shimeng Yu, Yexin Deng, Bin Gao, Peng Huang, Bing Chen, Xiaoyan Liu, Jinfeng Kang, Hong Yu Chen, Zizhen Jiang, H. S Philip Wong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

Design guidelines were proposed to evaluate and optimize the 3D RRAM cross-point architecture by a full-size 3D circuit simulation in SPICE. The performance metrics that were evaluated include the write/read margin, access latency, energy consumption per programming, and the density per bit. Different 3D cross-point architecture including the horizontally stacked or the vertically stacked structure were compared in terms of these metrics, revealing the advantages of the vertical RRAM structure. Then the scaling trend of the vertical RRAM based 3D array with respect to the scaling of lateral feature size, vertical electrode thickness and vertical isolation layer thickness were evaluated. The design parameters that affect the scaling trend include the metal interconnect resistance, RRAM on-state cell resistance (or the nonlinearity of the I-V). The design trade-offs are discussed considering those parameters constraints.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages421-424
Number of pages4
ISBN (Print)9781479934324
DOIs
StatePublished - 2014
Event2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia
Duration: Jun 1 2014Jun 5 2014

Other

Other2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
CountryAustralia
CityMelbourne, VIC
Period6/1/146/5/14

Fingerprint

Circuit simulation
SPICE
Energy utilization
Electrodes
RRAM
Metals

Keywords

  • 3D RRAM
  • cross-point array
  • design trade-off
  • SPICE simulation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Yu, S., Deng, Y., Gao, B., Huang, P., Chen, B., Liu, X., ... Wong, H. S. P. (2014). Design guidelines for 3D RRAM cross-point architecture. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 421-424). [6865155] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2014.6865155

Design guidelines for 3D RRAM cross-point architecture. / Yu, Shimeng; Deng, Yexin; Gao, Bin; Huang, Peng; Chen, Bing; Liu, Xiaoyan; Kang, Jinfeng; Chen, Hong Yu; Jiang, Zizhen; Wong, H. S Philip.

Proceedings - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 2014. p. 421-424 6865155.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yu, S, Deng, Y, Gao, B, Huang, P, Chen, B, Liu, X, Kang, J, Chen, HY, Jiang, Z & Wong, HSP 2014, Design guidelines for 3D RRAM cross-point architecture. in Proceedings - IEEE International Symposium on Circuits and Systems., 6865155, Institute of Electrical and Electronics Engineers Inc., pp. 421-424, 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014, Melbourne, VIC, Australia, 6/1/14. https://doi.org/10.1109/ISCAS.2014.6865155
Yu S, Deng Y, Gao B, Huang P, Chen B, Liu X et al. Design guidelines for 3D RRAM cross-point architecture. In Proceedings - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc. 2014. p. 421-424. 6865155 https://doi.org/10.1109/ISCAS.2014.6865155
Yu, Shimeng ; Deng, Yexin ; Gao, Bin ; Huang, Peng ; Chen, Bing ; Liu, Xiaoyan ; Kang, Jinfeng ; Chen, Hong Yu ; Jiang, Zizhen ; Wong, H. S Philip. / Design guidelines for 3D RRAM cross-point architecture. Proceedings - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 2014. pp. 421-424
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