@inproceedings{ef6ec95cddad446582e94d14465fbb0b,
title = "Design guidelines for 3D RRAM cross-point architecture",
abstract = "Design guidelines were proposed to evaluate and optimize the 3D RRAM cross-point architecture by a full-size 3D circuit simulation in SPICE. The performance metrics that were evaluated include the write/read margin, access latency, energy consumption per programming, and the density per bit. Different 3D cross-point architecture including the horizontally stacked or the vertically stacked structure were compared in terms of these metrics, revealing the advantages of the vertical RRAM structure. Then the scaling trend of the vertical RRAM based 3D array with respect to the scaling of lateral feature size, vertical electrode thickness and vertical isolation layer thickness were evaluated. The design parameters that affect the scaling trend include the metal interconnect resistance, RRAM on-state cell resistance (or the nonlinearity of the I-V). The design trade-offs are discussed considering those parameters constraints.",
keywords = "3D RRAM, SPICE simulation, cross-point array, design trade-off",
author = "Shimeng Yu and Yexin Deng and Bin Gao and Peng Huang and Bing Chen and Xiaoyan Liu and Jinfeng Kang and Chen, {Hong Yu} and Zizhen Jiang and Wong, {H. S Philip}",
year = "2014",
month = jan,
day = "1",
doi = "10.1109/ISCAS.2014.6865155",
language = "English (US)",
isbn = "9781479934324",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "421--424",
booktitle = "2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014",
note = "2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 ; Conference date: 01-06-2014 Through 05-06-2014",
}