Design and synthesis of ultralow energy spin-memristor threshold logic

Deliang Fan, Mrigank Sharad, Kaushik Roy

Research output: Contribution to journalArticlepeer-review

30 Scopus citations

Abstract

A threshold logic gate performs weighted sum of multiple inputs and compares the sum with a threshold. We propose spin-memeristor threshold logic (SMTL) gates, which employ a memristive cross-bar array to perform current-mode summation of binary inputs, whereas the low-voltage fast-switching spintronic threshold devices carry out the threshold operation in an energy efficient manner. Field-programmable SMTL gate arrays can operate at a small terminal voltage of ∼50 mV, resulting in ultralow power consumption in gates as well as programmable interconnect networks. We evaluate the performance of SMTL using threshold logic synthesis. Results for common benchmarks show that SMTL-based programmable logic hardware can be more than 100 × energy efficient than the state-of-the-art CMOS field-programmable gate array.

Original languageEnglish (US)
Article number6776526
Pages (from-to)574-583
Number of pages10
JournalIEEE Transactions on Nanotechnology
Volume13
Issue number3
DOIs
StatePublished - May 2014
Externally publishedYes

Keywords

  • Boolean functions
  • magnetic domains
  • memristor
  • nanotechnology
  • programmable logic arrays
  • threshold logic (TL)

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Design and synthesis of ultralow energy spin-memristor threshold logic'. Together they form a unique fingerprint.

Cite this