TY - GEN
T1 - CoSPARSE
T2 - 58th ACM/IEEE Design Automation Conference, DAC 2021
AU - Feng, Siying
AU - Sun, Jiawen
AU - Pal, Subhankar
AU - He, Xin
AU - Kaszyk, Kuba
AU - Park, Dong Hyeon
AU - Morton, Magnus
AU - Mudge, Trevor
AU - Cole, Murray
AU - O'Boyle, Michael
AU - Chakrabarti, Chaitali
AU - Dreslinski, Ronald
N1 - Publisher Copyright:
© 2021 IEEE.
PY - 2021/12/5
Y1 - 2021/12/5
N2 - Sparse matrix-vector multiplication (SpMV) is a critical building block for iterative graph analytics algorithms. Typically, such algorithms have a varying active vertex set across iterations. This variability has been used to improve performance by either dynamically switching algorithms between iterations (software) or designing custom accelerators (hardware) for graph analytics algorithms. In this work, we propose a novel framework, CoSPARSE, that employs hardware and software reconfiguration as a synergistic solution to accelerate SpMV-based graph analytics algorithms. Building on previously proposed general-purpose reconfigurable hardware, we implement CoSPARSE as a software layer, abstracting the hardware as a specialized SpMV accelerator. CoSPARSE dynamically selects software and hardware configurations for each iteration and achieves a maximum speedup of 2.0 × compared to the naïve implementation with no reconfiguration. Across a suite of graph algorithms, CoSPARSE outperforms a state-of-the-art shared memory framework, Ligra, on a Xeon CPU with up to 3.51 × better performance and 877 × better energy efficiency.
AB - Sparse matrix-vector multiplication (SpMV) is a critical building block for iterative graph analytics algorithms. Typically, such algorithms have a varying active vertex set across iterations. This variability has been used to improve performance by either dynamically switching algorithms between iterations (software) or designing custom accelerators (hardware) for graph analytics algorithms. In this work, we propose a novel framework, CoSPARSE, that employs hardware and software reconfiguration as a synergistic solution to accelerate SpMV-based graph analytics algorithms. Building on previously proposed general-purpose reconfigurable hardware, we implement CoSPARSE as a software layer, abstracting the hardware as a specialized SpMV accelerator. CoSPARSE dynamically selects software and hardware configurations for each iteration and achieves a maximum speedup of 2.0 × compared to the naïve implementation with no reconfiguration. Across a suite of graph algorithms, CoSPARSE outperforms a state-of-the-art shared memory framework, Ligra, on a Xeon CPU with up to 3.51 × better performance and 877 × better energy efficiency.
UR - http://www.scopus.com/inward/record.url?scp=85119438949&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85119438949&partnerID=8YFLogxK
U2 - 10.1109/DAC18074.2021.9586114
DO - 10.1109/DAC18074.2021.9586114
M3 - Conference contribution
AN - SCOPUS:85119438949
T3 - Proceedings - Design Automation Conference
SP - 949
EP - 954
BT - 2021 58th ACM/IEEE Design Automation Conference, DAC 2021
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 5 December 2021 through 9 December 2021
ER -