Compact modeling and simulation of accelerated circuit aging

Devyani Patra, Jiayang Zhang, Runsheng Wang, Mehdi Katoozi, Ethan H. Cannon, Ru Huang, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Accelerated aging becomes progressively pronounced in various circuits, due to the feedback between circuit operation and aging effects, especially HCI. To predict this behavior, the conventional method requires iterative simulations to track the elevated degradation rate, which is expensive in computation. In this paper, a compact model is derived for accelerated aging. By analyzing the underlying mechanism, the new model connects the degradation rate with both reliability physics and circuit topology. It is compatible with circuit simulation, general for design conditions, and efficient in long-term prediction. The new model is validated by silicon data at 65nm, 28nm, and 16/14nm technologies, demonstrating its scalability and effectiveness. Furthermore, it is applied to several benchmark circuits to illustrate the importance of accelerated aging.

Original languageEnglish (US)
Title of host publication2018 IEEE Custom Integrated Circuits Conference, CICC 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-4
Number of pages4
ISBN (Electronic)9781538624838
DOIs
StatePublished - May 9 2018
Externally publishedYes
Event2018 IEEE Custom Integrated Circuits Conference, CICC 2018 - San Diego, United States
Duration: Apr 8 2018Apr 11 2018

Other

Other2018 IEEE Custom Integrated Circuits Conference, CICC 2018
CountryUnited States
CitySan Diego
Period4/8/184/11/18

Fingerprint

Aging of materials
Networks (circuits)
Degradation
Electric network topology
Circuit simulation
Silicon
Human computer interaction
Iterative methods
Scalability
Physics
Feedback

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Patra, D., Zhang, J., Wang, R., Katoozi, M., Cannon, E. H., Huang, R., & Cao, Y. (2018). Compact modeling and simulation of accelerated circuit aging. In 2018 IEEE Custom Integrated Circuits Conference, CICC 2018 (pp. 1-4). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2018.8357063

Compact modeling and simulation of accelerated circuit aging. / Patra, Devyani; Zhang, Jiayang; Wang, Runsheng; Katoozi, Mehdi; Cannon, Ethan H.; Huang, Ru; Cao, Yu.

2018 IEEE Custom Integrated Circuits Conference, CICC 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 1-4.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Patra, D, Zhang, J, Wang, R, Katoozi, M, Cannon, EH, Huang, R & Cao, Y 2018, Compact modeling and simulation of accelerated circuit aging. in 2018 IEEE Custom Integrated Circuits Conference, CICC 2018. Institute of Electrical and Electronics Engineers Inc., pp. 1-4, 2018 IEEE Custom Integrated Circuits Conference, CICC 2018, San Diego, United States, 4/8/18. https://doi.org/10.1109/CICC.2018.8357063
Patra D, Zhang J, Wang R, Katoozi M, Cannon EH, Huang R et al. Compact modeling and simulation of accelerated circuit aging. In 2018 IEEE Custom Integrated Circuits Conference, CICC 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 1-4 https://doi.org/10.1109/CICC.2018.8357063
Patra, Devyani ; Zhang, Jiayang ; Wang, Runsheng ; Katoozi, Mehdi ; Cannon, Ethan H. ; Huang, Ru ; Cao, Yu. / Compact modeling and simulation of accelerated circuit aging. 2018 IEEE Custom Integrated Circuits Conference, CICC 2018. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 1-4
@inproceedings{f71fe9836f454e94a4f9935864ff9acd,
title = "Compact modeling and simulation of accelerated circuit aging",
abstract = "Accelerated aging becomes progressively pronounced in various circuits, due to the feedback between circuit operation and aging effects, especially HCI. To predict this behavior, the conventional method requires iterative simulations to track the elevated degradation rate, which is expensive in computation. In this paper, a compact model is derived for accelerated aging. By analyzing the underlying mechanism, the new model connects the degradation rate with both reliability physics and circuit topology. It is compatible with circuit simulation, general for design conditions, and efficient in long-term prediction. The new model is validated by silicon data at 65nm, 28nm, and 16/14nm technologies, demonstrating its scalability and effectiveness. Furthermore, it is applied to several benchmark circuits to illustrate the importance of accelerated aging.",
author = "Devyani Patra and Jiayang Zhang and Runsheng Wang and Mehdi Katoozi and Cannon, {Ethan H.} and Ru Huang and Yu Cao",
year = "2018",
month = "5",
day = "9",
doi = "10.1109/CICC.2018.8357063",
language = "English (US)",
pages = "1--4",
booktitle = "2018 IEEE Custom Integrated Circuits Conference, CICC 2018",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - GEN

T1 - Compact modeling and simulation of accelerated circuit aging

AU - Patra, Devyani

AU - Zhang, Jiayang

AU - Wang, Runsheng

AU - Katoozi, Mehdi

AU - Cannon, Ethan H.

AU - Huang, Ru

AU - Cao, Yu

PY - 2018/5/9

Y1 - 2018/5/9

N2 - Accelerated aging becomes progressively pronounced in various circuits, due to the feedback between circuit operation and aging effects, especially HCI. To predict this behavior, the conventional method requires iterative simulations to track the elevated degradation rate, which is expensive in computation. In this paper, a compact model is derived for accelerated aging. By analyzing the underlying mechanism, the new model connects the degradation rate with both reliability physics and circuit topology. It is compatible with circuit simulation, general for design conditions, and efficient in long-term prediction. The new model is validated by silicon data at 65nm, 28nm, and 16/14nm technologies, demonstrating its scalability and effectiveness. Furthermore, it is applied to several benchmark circuits to illustrate the importance of accelerated aging.

AB - Accelerated aging becomes progressively pronounced in various circuits, due to the feedback between circuit operation and aging effects, especially HCI. To predict this behavior, the conventional method requires iterative simulations to track the elevated degradation rate, which is expensive in computation. In this paper, a compact model is derived for accelerated aging. By analyzing the underlying mechanism, the new model connects the degradation rate with both reliability physics and circuit topology. It is compatible with circuit simulation, general for design conditions, and efficient in long-term prediction. The new model is validated by silicon data at 65nm, 28nm, and 16/14nm technologies, demonstrating its scalability and effectiveness. Furthermore, it is applied to several benchmark circuits to illustrate the importance of accelerated aging.

UR - http://www.scopus.com/inward/record.url?scp=85048086299&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85048086299&partnerID=8YFLogxK

U2 - 10.1109/CICC.2018.8357063

DO - 10.1109/CICC.2018.8357063

M3 - Conference contribution

AN - SCOPUS:85048086299

SP - 1

EP - 4

BT - 2018 IEEE Custom Integrated Circuits Conference, CICC 2018

PB - Institute of Electrical and Electronics Engineers Inc.

ER -