TY - GEN
T1 - Compact modeling and simulation of accelerated circuit aging
AU - Patra, Devyani
AU - Zhang, Jiayang
AU - Wang, Runsheng
AU - Katoozi, Mehdi
AU - Cannon, Ethan H.
AU - Huang, Ru
AU - Cao, Yu
N1 - Funding Information:
VI. ACKNOWLEDGEMENT This work was supported in part by DARPA contract HR0011-16-C-0041. The views, opinions, and/or findings expressed are those of the author(s) and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government. VII. REFERENCES
Publisher Copyright:
© 2018 IEEE.
PY - 2018/5/9
Y1 - 2018/5/9
N2 - Accelerated aging becomes progressively pronounced in various circuits, due to the feedback between circuit operation and aging effects, especially HCI. To predict this behavior, the conventional method requires iterative simulations to track the elevated degradation rate, which is expensive in computation. In this paper, a compact model is derived for accelerated aging. By analyzing the underlying mechanism, the new model connects the degradation rate with both reliability physics and circuit topology. It is compatible with circuit simulation, general for design conditions, and efficient in long-term prediction. The new model is validated by silicon data at 65nm, 28nm, and 16/14nm technologies, demonstrating its scalability and effectiveness. Furthermore, it is applied to several benchmark circuits to illustrate the importance of accelerated aging.
AB - Accelerated aging becomes progressively pronounced in various circuits, due to the feedback between circuit operation and aging effects, especially HCI. To predict this behavior, the conventional method requires iterative simulations to track the elevated degradation rate, which is expensive in computation. In this paper, a compact model is derived for accelerated aging. By analyzing the underlying mechanism, the new model connects the degradation rate with both reliability physics and circuit topology. It is compatible with circuit simulation, general for design conditions, and efficient in long-term prediction. The new model is validated by silicon data at 65nm, 28nm, and 16/14nm technologies, demonstrating its scalability and effectiveness. Furthermore, it is applied to several benchmark circuits to illustrate the importance of accelerated aging.
UR - http://www.scopus.com/inward/record.url?scp=85048086299&partnerID=8YFLogxK
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U2 - 10.1109/CICC.2018.8357063
DO - 10.1109/CICC.2018.8357063
M3 - Conference contribution
AN - SCOPUS:85048086299
T3 - 2018 IEEE Custom Integrated Circuits Conference, CICC 2018
SP - 1
EP - 4
BT - 2018 IEEE Custom Integrated Circuits Conference, CICC 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2018 IEEE Custom Integrated Circuits Conference, CICC 2018
Y2 - 8 April 2018 through 11 April 2018
ER -