Circuit simulation of threshold-voltage degradation in a-Si:H TFTs fabricated at 175 °C

Rahul Shringarpure; Sameer Venugopal; Zi Li; Lawrence T. Clark; David Allee; Edward Bawolek; Daniel Toy

doi:10.1109/TED.2007.899667

Circuit simulation of threshold-voltage degradation in a-Si:H TFTs fabricated at 175 °C

Rahul Shringarpure, Sameer Venugopal, Zi Li, Lawrence T. Clark, David Allee, Edward Bawolek, Daniel Toy

Research output: Contribution to journal › Article › peer-review

19 Scopus citations

Abstract

This brief presents a novel approach to modeling gate bias-induced threshold-voltage (V_th) degradation in hydrogenated amorphous silicon thin-film transistors (TFTs). The Vth degradation model is added to the SPICE 3.0 TFT device model to obtain a composite model and is verified by comparing the simulated V_th shift with measured data in a TFT latch circuit.

Original language	English (US)
Pages (from-to)	1781-1783
Number of pages	3
Journal	IEEE Transactions on Electron Devices
Volume	54
Issue number	7
DOIs	https://doi.org/10.1109/TED.2007.899667
State	Published - Jul 2007

Keywords

Circuit simulation
Display technology
Hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT)
SPICE
Threshold-voltage degradation

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/TED.2007.899667

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title = "Circuit simulation of threshold-voltage degradation in a-Si:H TFTs fabricated at 175 °C",

abstract = "This brief presents a novel approach to modeling gate bias-induced threshold-voltage (Vth) degradation in hydrogenated amorphous silicon thin-film transistors (TFTs). The Vth degradation model is added to the SPICE 3.0 TFT device model to obtain a composite model and is verified by comparing the simulated Vth shift with measured data in a TFT latch circuit.",

keywords = "Circuit simulation, Display technology, Hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT), SPICE, Threshold-voltage degradation",

author = "Rahul Shringarpure and Sameer Venugopal and Zi Li and Clark, {Lawrence T.} and David Allee and Edward Bawolek and Daniel Toy",

note = "Funding Information: Manuscript received November 9, 2006; revised April 20, 2006. This work was supported by the Army Research Laboratory under Cooperative Agreement W911NG-04-2-0005. The review of this brief was arranged by Editor M.A. Shibib.",

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language = "English (US)",

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T1 - Circuit simulation of threshold-voltage degradation in a-Si:H TFTs fabricated at 175 °C

AU - Shringarpure, Rahul

AU - Venugopal, Sameer

AU - Li, Zi

AU - Clark, Lawrence T.

AU - Allee, David

AU - Bawolek, Edward

AU - Toy, Daniel

N1 - Funding Information: Manuscript received November 9, 2006; revised April 20, 2006. This work was supported by the Army Research Laboratory under Cooperative Agreement W911NG-04-2-0005. The review of this brief was arranged by Editor M.A. Shibib.

PY - 2007/7

Y1 - 2007/7

N2 - This brief presents a novel approach to modeling gate bias-induced threshold-voltage (Vth) degradation in hydrogenated amorphous silicon thin-film transistors (TFTs). The Vth degradation model is added to the SPICE 3.0 TFT device model to obtain a composite model and is verified by comparing the simulated Vth shift with measured data in a TFT latch circuit.

AB - This brief presents a novel approach to modeling gate bias-induced threshold-voltage (Vth) degradation in hydrogenated amorphous silicon thin-film transistors (TFTs). The Vth degradation model is added to the SPICE 3.0 TFT device model to obtain a composite model and is verified by comparing the simulated Vth shift with measured data in a TFT latch circuit.

KW - Circuit simulation

KW - Display technology

KW - Hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT)

KW - SPICE

KW - Threshold-voltage degradation

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Circuit simulation of threshold-voltage degradation in a-Si:H TFTs fabricated at 175 °C

Abstract

Keywords

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