Circuit simulation of threshold-voltage degradation in a-Si:H TFTs fabricated at 175 °C

Rahul Shringarpure, Sameer Venugopal, Zi Li, Lawrence T. Clark, David Allee, Edward Bawolek, Daniel Toy

Research output: Contribution to journalArticle

17 Scopus citations

Abstract

This brief presents a novel approach to modeling gate bias-induced threshold-voltage (Vth) degradation in hydrogenated amorphous silicon thin-film transistors (TFTs). The Vth degradation model is added to the SPICE 3.0 TFT device model to obtain a composite model and is verified by comparing the simulated Vth shift with measured data in a TFT latch circuit.

Original languageEnglish (US)
Pages (from-to)1781-1783
Number of pages3
JournalIEEE Transactions on Electron Devices
Volume54
Issue number7
DOIs
StatePublished - Jul 1 2007

Keywords

  • Circuit simulation
  • Display technology
  • Hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT)
  • SPICE
  • Threshold-voltage degradation

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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