This brief presents a novel approach to modeling gate bias-induced threshold-voltage (Vth) degradation in hydrogenated amorphous silicon thin-film transistors (TFTs). The Vth degradation model is added to the SPICE 3.0 TFT device model to obtain a composite model and is verified by comparing the simulated Vth shift with measured data in a TFT latch circuit.
- Circuit simulation
- Display technology
- Hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT)
- Threshold-voltage degradation
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering