Abstract
Parasitic field oxide transistors are affected by ionizing radiation, becoming active circuit elements leading to loss of device isolation. Test structures are designed, fabricated and characterized allowing analysis of parasitic device layout geometries. Accurate modeling of parasitic devices through determination of effective width/length ratios supports compact model development for use in radiation-hardening-by-design activities.
Original language | English (US) |
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Article number | 6054044 |
Pages (from-to) | 2863-2870 |
Number of pages | 8 |
Journal | IEEE Transactions on Nuclear Science |
Volume | 58 |
Issue number | 6 PART 1 |
DOIs | |
State | Published - Dec 2011 |
Keywords
- Interdevice leakage
- local oxidation of silicon (LOCOS)
- oxide trapped charge
- radiation
- total ionizing dose (TID)
ASJC Scopus subject areas
- Nuclear and High Energy Physics
- Nuclear Energy and Engineering
- Electrical and Electronic Engineering