TY - JOUR
T1 - Architecture-aware LDPC code design for multiprocessor software defined radio systems
AU - Zhu, Yuming
AU - Chakrabarti, Chaitali
N1 - Funding Information:
Manuscript received August 27, 2008; accepted March 30, 2009. First published May 05, 2009; current version published August 12, 2009. The associate editor coordinating the review of this manuscript and approving it for publication was Prof. An-Yeu Wu. This work is based on Ph.D. research at Arizona State University, Tempe. This work was supported in part by the NSF by Grants NSF-ITR 0325761 and NSF CSR-EHS 0615135.
PY - 2009
Y1 - 2009
N2 - This paper presents a general procedure for designing low density parity check (LDPC) codes for multiprocessor software defined radio platforms. Our approach is to design the LDPC code to match the constraints imposed by the hardware architecture, without compromising on the communication performance. The proposed architecture-aware code design procedure involves feature identification, code construction and verification. We demonstrate the effectiveness of our procedure for three cases. If the local memory of the processor is small and it can only process one horizontally partitioned submatrix at a time, we show how the code can be constructed so that the traffic to the global memories is reduced by 2X. If the row weight of the matrix is large and each processor processes a vertically partitioned submatrix, we show how the matrix can be constructed so that the computational load is evenly distributed among the processors. If the processors have no storage capability and all data is stored in global memories, then for the case when all traffic is through a multistage interconnection network, we show how code construction can be used to significantly reduce the number of routing conflicts. In all three cases, the resulting LDPC codes can not only be mapped efficiently onto the multiprocessor platform but also have very good frame error performance.
AB - This paper presents a general procedure for designing low density parity check (LDPC) codes for multiprocessor software defined radio platforms. Our approach is to design the LDPC code to match the constraints imposed by the hardware architecture, without compromising on the communication performance. The proposed architecture-aware code design procedure involves feature identification, code construction and verification. We demonstrate the effectiveness of our procedure for three cases. If the local memory of the processor is small and it can only process one horizontally partitioned submatrix at a time, we show how the code can be constructed so that the traffic to the global memories is reduced by 2X. If the row weight of the matrix is large and each processor processes a vertically partitioned submatrix, we show how the matrix can be constructed so that the computational load is evenly distributed among the processors. If the processors have no storage capability and all data is stored in global memories, then for the case when all traffic is through a multistage interconnection network, we show how code construction can be used to significantly reduce the number of routing conflicts. In all three cases, the resulting LDPC codes can not only be mapped efficiently onto the multiprocessor platform but also have very good frame error performance.
KW - Decoder
KW - Encoder
KW - Low-density parity check (LDPC)
KW - Multiprocessor
KW - Software defined radio (SDR)
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U2 - 10.1109/TSP.2009.2022356
DO - 10.1109/TSP.2009.2022356
M3 - Article
AN - SCOPUS:69349102330
SN - 1053-587X
VL - 57
SP - 3679
EP - 3692
JO - IEEE Transactions on Signal Processing
JF - IEEE Transactions on Signal Processing
IS - 9
ER -