@inproceedings{ce5ad6245ac046159eb9b53a62782d92,
title = "Application specific reconfigurable architecture design",
abstract = "A lookup table (LUT) based packing mechanism has been presented as part of the application specific reconfigurable architecture design methodology proposed in earlier work. In addition to routability driven cost metrics defined by other researchers, packing mechanism prioritizes nets that lead to reduction of input/output pins that are within the fan-in fan-out distance. Existing approaches treat the number of intersecting nets as positive gain during packing and ignore the wiring requirement growth within the cluster being formed. New packing algorithm employs average interconnection length estimation obtained through Rent's Rule in order to incorporate the wiring requirement into the cost function. This approach provides on average 28% reduction in number of nets and 26% reduction on number of tracks used compared to the state of the art approaches. Results will lead to significant amount of savings in switching complexity; hence contribute to reduction in power consumption and increase the processing speed.",
keywords = "Fpga, Look up table, Packing, Routing",
author = "A. Akoglu and Sethuraman Panchanathan",
year = "2005",
month = dec,
day = "1",
language = "English (US)",
isbn = "9781932415742",
series = "Proceedings of the 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'05",
pages = "247--250",
booktitle = "Proceedings of the 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'05",
note = "2005 5th International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'05 ; Conference date: 27-06-2005 Through 30-06-2005",
}