TY - GEN
T1 - Analytical router modeling for networks-on-chip performance analysis
AU - Ogras, Umit Y.
AU - Marculescu, Radu
PY - 2007
Y1 - 2007
N2 - Networks-on-Chip (NoCs) have recently emerged as a scalable alternative to classical bus and point-to-point architectures. To date, performance evaluation of NoC designs is largely based on simulation which, besides being extremely slow, provides little insight on how different design parameters affect the actual network performance. Therefore, it is practically impossible to use simulation for optimization purposes. In this paper, we first present a generalized router model and then utilize this novel model for doing NoC performance analysis. The proposed model can be used not only to obtain fast and accurate performance estimates, but also to guide the NoC design process within an optimization loop. The accuracy of our approach and its practical use is illustrated through extensive simulation results.
AB - Networks-on-Chip (NoCs) have recently emerged as a scalable alternative to classical bus and point-to-point architectures. To date, performance evaluation of NoC designs is largely based on simulation which, besides being extremely slow, provides little insight on how different design parameters affect the actual network performance. Therefore, it is practically impossible to use simulation for optimization purposes. In this paper, we first present a generalized router model and then utilize this novel model for doing NoC performance analysis. The proposed model can be used not only to obtain fast and accurate performance estimates, but also to guide the NoC design process within an optimization loop. The accuracy of our approach and its practical use is illustrated through extensive simulation results.
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U2 - 10.1109/DATE.2007.364440
DO - 10.1109/DATE.2007.364440
M3 - Conference contribution
AN - SCOPUS:34548304654
SN - 3981080122
SN - 9783981080124
T3 - Proceedings -Design, Automation and Test in Europe, DATE
SP - 1096
EP - 1101
BT - Proceedings - 2007 Design, Automation and Test in Europe Conference and Exhibition, DATE 2007
T2 - 2007 Design, Automation and Test in Europe Conference and Exhibition
Y2 - 16 April 2007 through 20 April 2007
ER -