Analytical router modeling for networks-on-chip performance analysis

Umit Y. Ogras, Radu Marculescu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

72 Scopus citations

Abstract

Networks-on-Chip (NoCs) have recently emerged as a scalable alternative to classical bus and point-to-point architectures. To date, performance evaluation of NoC designs is largely based on simulation which, besides being extremely slow, provides little insight on how different design parameters affect the actual network performance. Therefore, it is practically impossible to use simulation for optimization purposes. In this paper, we first present a generalized router model and then utilize this novel model for doing NoC performance analysis. The proposed model can be used not only to obtain fast and accurate performance estimates, but also to guide the NoC design process within an optimization loop. The accuracy of our approach and its practical use is illustrated through extensive simulation results.

Original languageEnglish (US)
Title of host publicationProceedings - 2007 Design, Automation and Test in Europe Conference and Exhibition, DATE 2007
Pages1096-1101
Number of pages6
DOIs
StatePublished - Sep 4 2007
Externally publishedYes
Event2007 Design, Automation and Test in Europe Conference and Exhibition - Nice Acropolis, France
Duration: Apr 16 2007Apr 20 2007

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
ISSN (Print)1530-1591

Other

Other2007 Design, Automation and Test in Europe Conference and Exhibition
CountryFrance
CityNice Acropolis
Period4/16/074/20/07

ASJC Scopus subject areas

  • Engineering(all)

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    Ogras, U. Y., & Marculescu, R. (2007). Analytical router modeling for networks-on-chip performance analysis. In Proceedings - 2007 Design, Automation and Test in Europe Conference and Exhibition, DATE 2007 (pp. 1096-1101). [4211950] (Proceedings -Design, Automation and Test in Europe, DATE). https://doi.org/10.1109/DATE.2007.364440