Analytical performance models for RLC interconnects and application to clock optimization

Xuejue Huang, Yu Cao, Dennis Sylvester, Tsu Jae King, Chenming Hu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

A novel analytical approach for RLC interconnect performance analysis is developed. Using the gate and line geometries as inputs, we derive closed-form expressions for propagation delay, rise time, and voltage overshoot at both the driver output and the far end of the interconnect. This analytical approach enables fast and accurate RLC interconnect analysis and design optimization. Application to clock interconnect optimization is demonstrated and design guidelines are proposed.

Original languageEnglish (US)
Title of host publicationProceedings of the Annual IEEE International ASIC Conference and Exhibit
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages353-357
Number of pages5
Volume2002-January
ISBN (Print)0780374940
DOIs
StatePublished - 2002
Externally publishedYes
Event15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 - Rochester, United States
Duration: Sep 25 2002Sep 28 2002

Other

Other15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
CountryUnited States
CityRochester
Period9/25/029/28/02

Fingerprint

Clocks
Time delay
Geometry
Electric potential
Design optimization

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Huang, X., Cao, Y., Sylvester, D., King, T. J., & Hu, C. (2002). Analytical performance models for RLC interconnects and application to clock optimization. In Proceedings of the Annual IEEE International ASIC Conference and Exhibit (Vol. 2002-January, pp. 353-357). [1158084] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASIC.2002.1158084

Analytical performance models for RLC interconnects and application to clock optimization. / Huang, Xuejue; Cao, Yu; Sylvester, Dennis; King, Tsu Jae; Hu, Chenming.

Proceedings of the Annual IEEE International ASIC Conference and Exhibit. Vol. 2002-January Institute of Electrical and Electronics Engineers Inc., 2002. p. 353-357 1158084.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Huang, X, Cao, Y, Sylvester, D, King, TJ & Hu, C 2002, Analytical performance models for RLC interconnects and application to clock optimization. in Proceedings of the Annual IEEE International ASIC Conference and Exhibit. vol. 2002-January, 1158084, Institute of Electrical and Electronics Engineers Inc., pp. 353-357, 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002, Rochester, United States, 9/25/02. https://doi.org/10.1109/ASIC.2002.1158084
Huang X, Cao Y, Sylvester D, King TJ, Hu C. Analytical performance models for RLC interconnects and application to clock optimization. In Proceedings of the Annual IEEE International ASIC Conference and Exhibit. Vol. 2002-January. Institute of Electrical and Electronics Engineers Inc. 2002. p. 353-357. 1158084 https://doi.org/10.1109/ASIC.2002.1158084
Huang, Xuejue ; Cao, Yu ; Sylvester, Dennis ; King, Tsu Jae ; Hu, Chenming. / Analytical performance models for RLC interconnects and application to clock optimization. Proceedings of the Annual IEEE International ASIC Conference and Exhibit. Vol. 2002-January Institute of Electrical and Electronics Engineers Inc., 2002. pp. 353-357
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