TY - GEN
T1 - Analytical performance models for RLC interconnects and application to clock optimization
AU - Huang, Xuejue
AU - Cao, Yu
AU - Sylvester, Dennis
AU - King, Tsu Jae
AU - Hu, Chenming
N1 - Publisher Copyright:
© 2002 IEEE.
PY - 2002
Y1 - 2002
N2 - A novel analytical approach for RLC interconnect performance analysis is developed. Using the gate and line geometries as inputs, we derive closed-form expressions for propagation delay, rise time, and voltage overshoot at both the driver output and the far end of the interconnect. This analytical approach enables fast and accurate RLC interconnect analysis and design optimization. Application to clock interconnect optimization is demonstrated and design guidelines are proposed.
AB - A novel analytical approach for RLC interconnect performance analysis is developed. Using the gate and line geometries as inputs, we derive closed-form expressions for propagation delay, rise time, and voltage overshoot at both the driver output and the far end of the interconnect. This analytical approach enables fast and accurate RLC interconnect analysis and design optimization. Application to clock interconnect optimization is demonstrated and design guidelines are proposed.
UR - http://www.scopus.com/inward/record.url?scp=27544471932&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=27544471932&partnerID=8YFLogxK
U2 - 10.1109/ASIC.2002.1158084
DO - 10.1109/ASIC.2002.1158084
M3 - Conference contribution
AN - SCOPUS:27544471932
T3 - Proceedings of the Annual IEEE International ASIC Conference and Exhibit
SP - 353
EP - 357
BT - Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
A2 - Chickanosky, John
A2 - Krishnamurthy, Ram K.
A2 - Mukund, P.R.
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
Y2 - 25 September 2002 through 28 September 2002
ER -