### Abstract

We analyze the behavior of signal probabilities in logic circuits chosen from a statistically characterized population. The statistical parameters of the population are obtained from certain aggregate structural and logical characteristics of the circuit such as fanins, fanouts, and proportions of different types of gates. A circuit is first transformed into one consisting of only nand gates, inverters, and buffers. This transformation leads to a new classification of circuits, referred to as nor-type, or-type, nand-type and and-type, the particular type being determined by computing two parameters from the circuit specification. A functional relation between gate signal probabilities, primary input signal probabilities, and aggregate structural properties of a circuit is established. This allows the study of basic characteristics of signal probability and its limiting behavior when the number of levels increases. It is shown that the limiting behavior of signal probability depends on the fixed points of a function which is determined by the two parameters estimated from the circuit and the distribution of gate fanins. A recurrence relation also allows us to define a methodology for estimating the distribution of signal probabilities in different levels. The complexity of this technique is shown to be proportional to the number of levels in the circuit. Results of extensive experiments with ISCAS '85 benchmarks as well as other circuits indicate that the methods are applicable for fast estimation of gate signal probabilities in general circuits. Finally, this work provides a complete generalization of earlier work on relating aggregate structural characteristics of a circuit to its signal probability behavior.

Original language | English (US) |
---|---|

Pages (from-to) | 365-379 |

Number of pages | 15 |

Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |

Volume | 1 |

Issue number | 3 |

DOIs | |

State | Published - Sep 1993 |

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### ASJC Scopus subject areas

- Hardware and Architecture
- Electrical and Electronic Engineering

### Cite this

**Analysis of signal probability in logic circuits using stochastic models.** / Majumdar, Amitava; Vrudhula, Sarma.

Research output: Contribution to journal › Article

*IEEE Transactions on Very Large Scale Integration (VLSI) Systems*, vol. 1, no. 3, pp. 365-379. https://doi.org/10.1109/92.238448

}

TY - JOUR

T1 - Analysis of signal probability in logic circuits using stochastic models

AU - Majumdar, Amitava

AU - Vrudhula, Sarma

PY - 1993/9

Y1 - 1993/9

N2 - We analyze the behavior of signal probabilities in logic circuits chosen from a statistically characterized population. The statistical parameters of the population are obtained from certain aggregate structural and logical characteristics of the circuit such as fanins, fanouts, and proportions of different types of gates. A circuit is first transformed into one consisting of only nand gates, inverters, and buffers. This transformation leads to a new classification of circuits, referred to as nor-type, or-type, nand-type and and-type, the particular type being determined by computing two parameters from the circuit specification. A functional relation between gate signal probabilities, primary input signal probabilities, and aggregate structural properties of a circuit is established. This allows the study of basic characteristics of signal probability and its limiting behavior when the number of levels increases. It is shown that the limiting behavior of signal probability depends on the fixed points of a function which is determined by the two parameters estimated from the circuit and the distribution of gate fanins. A recurrence relation also allows us to define a methodology for estimating the distribution of signal probabilities in different levels. The complexity of this technique is shown to be proportional to the number of levels in the circuit. Results of extensive experiments with ISCAS '85 benchmarks as well as other circuits indicate that the methods are applicable for fast estimation of gate signal probabilities in general circuits. Finally, this work provides a complete generalization of earlier work on relating aggregate structural characteristics of a circuit to its signal probability behavior.

AB - We analyze the behavior of signal probabilities in logic circuits chosen from a statistically characterized population. The statistical parameters of the population are obtained from certain aggregate structural and logical characteristics of the circuit such as fanins, fanouts, and proportions of different types of gates. A circuit is first transformed into one consisting of only nand gates, inverters, and buffers. This transformation leads to a new classification of circuits, referred to as nor-type, or-type, nand-type and and-type, the particular type being determined by computing two parameters from the circuit specification. A functional relation between gate signal probabilities, primary input signal probabilities, and aggregate structural properties of a circuit is established. This allows the study of basic characteristics of signal probability and its limiting behavior when the number of levels increases. It is shown that the limiting behavior of signal probability depends on the fixed points of a function which is determined by the two parameters estimated from the circuit and the distribution of gate fanins. A recurrence relation also allows us to define a methodology for estimating the distribution of signal probabilities in different levels. The complexity of this technique is shown to be proportional to the number of levels in the circuit. Results of extensive experiments with ISCAS '85 benchmarks as well as other circuits indicate that the methods are applicable for fast estimation of gate signal probabilities in general circuits. Finally, this work provides a complete generalization of earlier work on relating aggregate structural characteristics of a circuit to its signal probability behavior.

UR - http://www.scopus.com/inward/record.url?scp=0027666397&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0027666397&partnerID=8YFLogxK

U2 - 10.1109/92.238448

DO - 10.1109/92.238448

M3 - Article

AN - SCOPUS:0027666397

VL - 1

SP - 365

EP - 379

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 3

ER -