Analysis of pulse signaling for low-power on-chip global bus design

Min Chen, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

Pulse signaling is proposed for on-chip global bus design to reduce dynamic power consumption. To maximize power saving, shorter pulse width and longer propagation length are preferred. In this work, a complete set of analytical models are developed for pulse propagation along RLC lines. These models connect line geometries and electrical properties of an input pulse with several important design metrics, such as delay, pulse width, maximum propagation length, and power saving. Excellent model accuracy is achieved as compared to SPICE simulations. These models can be easily implemented into design tools to facilitate the optimization of pulse signaling on lossy on-chip global buses. Furthermore, pulse signaling can be integrated with a time-division scheme to further reduce power consumption. Using the newly developed models, it is demonstrated that more than 70% dynamic power can be saved in this scheme in on-chip bus design.

Original languageEnglish (US)
Title of host publicationProceedings - International Symposium on Quality Electronic Design, ISQED
Pages401-406
Number of pages6
DOIs
StatePublished - 2006
Event7th International Symposium on Quality Electronic Design, ISQED 2006 - San Jose, CA, United States
Duration: Mar 27 2006Mar 29 2006

Other

Other7th International Symposium on Quality Electronic Design, ISQED 2006
CountryUnited States
CitySan Jose, CA
Period3/27/063/29/06

Fingerprint

Electric power utilization
SPICE
Analytical models
Electric properties
Geometry

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

Cite this

Chen, M., & Cao, Y. (2006). Analysis of pulse signaling for low-power on-chip global bus design. In Proceedings - International Symposium on Quality Electronic Design, ISQED (pp. 401-406). [1613170] https://doi.org/10.1109/ISQED.2006.27

Analysis of pulse signaling for low-power on-chip global bus design. / Chen, Min; Cao, Yu.

Proceedings - International Symposium on Quality Electronic Design, ISQED. 2006. p. 401-406 1613170.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Chen, M & Cao, Y 2006, Analysis of pulse signaling for low-power on-chip global bus design. in Proceedings - International Symposium on Quality Electronic Design, ISQED., 1613170, pp. 401-406, 7th International Symposium on Quality Electronic Design, ISQED 2006, San Jose, CA, United States, 3/27/06. https://doi.org/10.1109/ISQED.2006.27
Chen M, Cao Y. Analysis of pulse signaling for low-power on-chip global bus design. In Proceedings - International Symposium on Quality Electronic Design, ISQED. 2006. p. 401-406. 1613170 https://doi.org/10.1109/ISQED.2006.27
Chen, Min ; Cao, Yu. / Analysis of pulse signaling for low-power on-chip global bus design. Proceedings - International Symposium on Quality Electronic Design, ISQED. 2006. pp. 401-406
@inproceedings{a27ca5b0aedb4e7db9999e4686cb4fd6,
title = "Analysis of pulse signaling for low-power on-chip global bus design",
abstract = "Pulse signaling is proposed for on-chip global bus design to reduce dynamic power consumption. To maximize power saving, shorter pulse width and longer propagation length are preferred. In this work, a complete set of analytical models are developed for pulse propagation along RLC lines. These models connect line geometries and electrical properties of an input pulse with several important design metrics, such as delay, pulse width, maximum propagation length, and power saving. Excellent model accuracy is achieved as compared to SPICE simulations. These models can be easily implemented into design tools to facilitate the optimization of pulse signaling on lossy on-chip global buses. Furthermore, pulse signaling can be integrated with a time-division scheme to further reduce power consumption. Using the newly developed models, it is demonstrated that more than 70{\%} dynamic power can be saved in this scheme in on-chip bus design.",
author = "Min Chen and Yu Cao",
year = "2006",
doi = "10.1109/ISQED.2006.27",
language = "English (US)",
isbn = "0769525237",
pages = "401--406",
booktitle = "Proceedings - International Symposium on Quality Electronic Design, ISQED",

}

TY - GEN

T1 - Analysis of pulse signaling for low-power on-chip global bus design

AU - Chen, Min

AU - Cao, Yu

PY - 2006

Y1 - 2006

N2 - Pulse signaling is proposed for on-chip global bus design to reduce dynamic power consumption. To maximize power saving, shorter pulse width and longer propagation length are preferred. In this work, a complete set of analytical models are developed for pulse propagation along RLC lines. These models connect line geometries and electrical properties of an input pulse with several important design metrics, such as delay, pulse width, maximum propagation length, and power saving. Excellent model accuracy is achieved as compared to SPICE simulations. These models can be easily implemented into design tools to facilitate the optimization of pulse signaling on lossy on-chip global buses. Furthermore, pulse signaling can be integrated with a time-division scheme to further reduce power consumption. Using the newly developed models, it is demonstrated that more than 70% dynamic power can be saved in this scheme in on-chip bus design.

AB - Pulse signaling is proposed for on-chip global bus design to reduce dynamic power consumption. To maximize power saving, shorter pulse width and longer propagation length are preferred. In this work, a complete set of analytical models are developed for pulse propagation along RLC lines. These models connect line geometries and electrical properties of an input pulse with several important design metrics, such as delay, pulse width, maximum propagation length, and power saving. Excellent model accuracy is achieved as compared to SPICE simulations. These models can be easily implemented into design tools to facilitate the optimization of pulse signaling on lossy on-chip global buses. Furthermore, pulse signaling can be integrated with a time-division scheme to further reduce power consumption. Using the newly developed models, it is demonstrated that more than 70% dynamic power can be saved in this scheme in on-chip bus design.

UR - http://www.scopus.com/inward/record.url?scp=56749100060&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=56749100060&partnerID=8YFLogxK

U2 - 10.1109/ISQED.2006.27

DO - 10.1109/ISQED.2006.27

M3 - Conference contribution

AN - SCOPUS:56749100060

SN - 0769525237

SN - 9780769525235

SP - 401

EP - 406

BT - Proceedings - International Symposium on Quality Electronic Design, ISQED

ER -