An integrated tool for analog test generation and fault simulation

Sule Ozev, A. Orailoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

High levels of design integration and increasing number of analog blocks within a system necessitate automated system-level analog test generation and fault simulation tools. We outline a methodology and toolset for specification-based automated test generation and fault simulation for analog circuits. Test generation is targeted at providing the highest coverage for each specified parameter. The flexibility of assigning analog test attributes is utilized for merging tests leading to test time reduction with no loss in test coverage. Further optimization in test time is obtained through fault simulations by selecting tests that provide adequate coverage in terms of several components and dropping the ones that do not provide additional coverage. The generated test set, fault and yield coverages in terms of each targeted parameter, and testability problems are reported by the tool.

Original languageEnglish (US)
Title of host publicationProceedings - International Symposium on Quality Electronic Design, ISQED
PublisherIEEE Computer Society
Pages267-272
Number of pages6
Volume2002-January
ISBN (Print)0769515614
DOIs
StatePublished - 2002
Externally publishedYes
Event3rd International Symposium on Quality Electronic Design, ISQED 2002 - San Jose, United States
Duration: Mar 18 2002Mar 21 2002

Other

Other3rd International Symposium on Quality Electronic Design, ISQED 2002
CountryUnited States
CitySan Jose
Period3/18/023/21/02

Fingerprint

Analog circuits
Merging
Specifications

Keywords

  • Analog circuits
  • Automatic testing
  • Circuit faults
  • Circuit simulation
  • Circuit testing
  • Computational modeling
  • Computer science
  • Computer simulation
  • Design engineering
  • System testing

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

Cite this

Ozev, S., & Orailoglu, A. (2002). An integrated tool for analog test generation and fault simulation. In Proceedings - International Symposium on Quality Electronic Design, ISQED (Vol. 2002-January, pp. 267-272). [996748] IEEE Computer Society. https://doi.org/10.1109/ISQED.2002.996748

An integrated tool for analog test generation and fault simulation. / Ozev, Sule; Orailoglu, A.

Proceedings - International Symposium on Quality Electronic Design, ISQED. Vol. 2002-January IEEE Computer Society, 2002. p. 267-272 996748.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ozev, S & Orailoglu, A 2002, An integrated tool for analog test generation and fault simulation. in Proceedings - International Symposium on Quality Electronic Design, ISQED. vol. 2002-January, 996748, IEEE Computer Society, pp. 267-272, 3rd International Symposium on Quality Electronic Design, ISQED 2002, San Jose, United States, 3/18/02. https://doi.org/10.1109/ISQED.2002.996748
Ozev S, Orailoglu A. An integrated tool for analog test generation and fault simulation. In Proceedings - International Symposium on Quality Electronic Design, ISQED. Vol. 2002-January. IEEE Computer Society. 2002. p. 267-272. 996748 https://doi.org/10.1109/ISQED.2002.996748
Ozev, Sule ; Orailoglu, A. / An integrated tool for analog test generation and fault simulation. Proceedings - International Symposium on Quality Electronic Design, ISQED. Vol. 2002-January IEEE Computer Society, 2002. pp. 267-272
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