Abstract
High levels of design integration and increasing number of analog blocks within a system necessitate automated system-level analog test generation and fault simulation tools. We outline a methodology and toolset for specification-based automated test generation and fault simulation for analog circuits. Test generation is targeted at providing the highest coverage for each specified parameter. The flexibility of assigning analog test attributes is utilized for merging tests leading to test time reduction with no loss in test coverage. Further optimization in test time is obtained through fault simulations by selecting tests that provide adequate coverage in terms of several components and dropping the ones that do not provide additional coverage. The generated test set, fault and yield coverages in terms of each targeted parameter, and testability problems are reported by the tool.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings - International Symposium on Quality Electronic Design, ISQED |
| Publisher | IEEE Computer Society |
| Pages | 267-272 |
| Number of pages | 6 |
| Volume | 2002-January |
| ISBN (Print) | 0769515614 |
| DOIs | |
| State | Published - 2002 |
| Externally published | Yes |
| Event | 3rd International Symposium on Quality Electronic Design, ISQED 2002 - San Jose, United States Duration: Mar 18 2002 → Mar 21 2002 |
Other
| Other | 3rd International Symposium on Quality Electronic Design, ISQED 2002 |
|---|---|
| Country/Territory | United States |
| City | San Jose |
| Period | 3/18/02 → 3/21/02 |
Keywords
- Analog circuits
- Automatic testing
- Circuit faults
- Circuit simulation
- Circuit testing
- Computational modeling
- Computer science
- Computer simulation
- Design engineering
- System testing
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
- Safety, Risk, Reliability and Quality