ALGEBRAIC MODEL OF FAULT-MASKING LOGIC CIRCUITS.

Thomas F. Schwab, Sik-Sang Yau

Research output: Contribution to journalArticle

7 Citations (Scopus)

Abstract

An algebraic model of fault-masking logic (FML) circuits, assuming bitwise logical operations and a separate single-valued coding system is presented. From this model, the necessary and sufficient conditions to construct FML circuits are derived, and the error-propagating and error-correcting characteristics of such FML circuits are defined in terms of a Boolean vector algebra and a syndrome-like function. The capabilities and limitations of FML circuits are characterized and several constructive techniques are explored. Optimum FML constructions are developed for correcting a maximum number of faults in a minimum number of logic levels for simple logic structures. For complex logic structures, these constructions apply but it is not known if they are optimum. In addition, the enhancement of FML circuits with fault-detecting capabilities is developed in the event that the error-correcting capabilities of FML circuits should be exceeded.

Original languageEnglish (US)
Pages (from-to)809-825
Number of pages17
JournalIEEE Transactions on Computers
VolumeC-32
Issue number9
StatePublished - Sep 1983
Externally publishedYes

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Logic circuits
Masking
Fault
Logic
Model
Vector algebra
Algebra
Single valued
Boolean algebra
Enhancement
Coding
Necessary Conditions
Sufficient Conditions

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

ALGEBRAIC MODEL OF FAULT-MASKING LOGIC CIRCUITS. / Schwab, Thomas F.; Yau, Sik-Sang.

In: IEEE Transactions on Computers, Vol. C-32, No. 9, 09.1983, p. 809-825.

Research output: Contribution to journalArticle

Schwab, Thomas F. ; Yau, Sik-Sang. / ALGEBRAIC MODEL OF FAULT-MASKING LOGIC CIRCUITS. In: IEEE Transactions on Computers. 1983 ; Vol. C-32, No. 9. pp. 809-825.
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