### Abstract

An algebraic model of fault-masking logic (FML) circuits, assuming bitwise logical operations and a separate single-valued coding system is presented. From this model, the necessary and sufficient conditions to construct FML circuits are derived, and the error-propagating and error-correcting characteristics of such FML circuits are defined in terms of a Boolean vector algebra and a syndrome-like function. The capabilities and limitations of FML circuits are characterized and several constructive techniques are explored. Optimum FML constructions are developed for correcting a maximum number of faults in a minimum number of logic levels for simple logic structures. For complex logic structures, these constructions apply but it is not known if they are optimum. In addition, the enhancement of FML circuits with fault-detecting capabilities is developed in the event that the error-correcting capabilities of FML circuits should be exceeded.

Original language | English (US) |
---|---|

Pages (from-to) | 809-825 |

Number of pages | 17 |

Journal | IEEE Transactions on Computers |

Volume | C-32 |

Issue number | 9 |

State | Published - Sep 1983 |

Externally published | Yes |

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### ASJC Scopus subject areas

- Hardware and Architecture
- Electrical and Electronic Engineering

### Cite this

*IEEE Transactions on Computers*,

*C-32*(9), 809-825.

**ALGEBRAIC MODEL OF FAULT-MASKING LOGIC CIRCUITS.** / Schwab, Thomas F.; Yau, Sik-Sang.

Research output: Contribution to journal › Article

*IEEE Transactions on Computers*, vol. C-32, no. 9, pp. 809-825.

}

TY - JOUR

T1 - ALGEBRAIC MODEL OF FAULT-MASKING LOGIC CIRCUITS.

AU - Schwab, Thomas F.

AU - Yau, Sik-Sang

PY - 1983/9

Y1 - 1983/9

N2 - An algebraic model of fault-masking logic (FML) circuits, assuming bitwise logical operations and a separate single-valued coding system is presented. From this model, the necessary and sufficient conditions to construct FML circuits are derived, and the error-propagating and error-correcting characteristics of such FML circuits are defined in terms of a Boolean vector algebra and a syndrome-like function. The capabilities and limitations of FML circuits are characterized and several constructive techniques are explored. Optimum FML constructions are developed for correcting a maximum number of faults in a minimum number of logic levels for simple logic structures. For complex logic structures, these constructions apply but it is not known if they are optimum. In addition, the enhancement of FML circuits with fault-detecting capabilities is developed in the event that the error-correcting capabilities of FML circuits should be exceeded.

AB - An algebraic model of fault-masking logic (FML) circuits, assuming bitwise logical operations and a separate single-valued coding system is presented. From this model, the necessary and sufficient conditions to construct FML circuits are derived, and the error-propagating and error-correcting characteristics of such FML circuits are defined in terms of a Boolean vector algebra and a syndrome-like function. The capabilities and limitations of FML circuits are characterized and several constructive techniques are explored. Optimum FML constructions are developed for correcting a maximum number of faults in a minimum number of logic levels for simple logic structures. For complex logic structures, these constructions apply but it is not known if they are optimum. In addition, the enhancement of FML circuits with fault-detecting capabilities is developed in the event that the error-correcting capabilities of FML circuits should be exceeded.

UR - http://www.scopus.com/inward/record.url?scp=0020815599&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0020815599&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0020815599

VL - C-32

SP - 809

EP - 825

JO - IEEE Transactions on Computers

JF - IEEE Transactions on Computers

SN - 0018-9340

IS - 9

ER -