An Algebraic Model of Fault-Masking Logic Circuits

In this paper, an algebraic model of fault-masking logic (FML) circuits, assuming bitwise logical operations and a separate single-valued coding system is presented. From this model, the necessary and sufficient conditions to construct FML circuits are derived, and the error-propagating and error-correcting characteristics of such FML circuits are defined in terms of a Boolean vector algebra and a syndrome-like function. The capabilities and limitations of FML circuits are characterized and several constructive techniques are explored. Optimum FML constructions are developed for correcting a maximum number of faults in a minimum number of logic levels for simple logic structures. For complex logic structures, these constructions apply but it is not known if they are optimum. In addition, the enhancement of FML circuits with fault-detecting capabilities is developed in the event that the error-correcting capabilities of FML circuits should be exceeded. FML concepts can potentially simplify the hardware and software recovery design of high availability systems because traditional maintenance and error-recovery procedures are not necessarily required. Several reliability comparisons to other fault-tolerant techniques indicate that properly designed FML circuits can achieve lower system down-time objectives with a much simpler and less costly maintenance strategy. The massive hardware redundancy requirements of FML constructions are not considered critical because of the emerging expectations of extremely high levels of integrated circuit technology.