Adaptively Biased Output Cap-Less NMOS LDO with 19 ns Settling-Time

Debashis Mandal, Chirag Desai, Bertan Bakkaloglu, Sayfe Kiaei

Research output: Contribution to journalArticlepeer-review

14 Scopus citations


This paper presents an output external capacitor-less, fully integrated, fast settling NMOS low-dropout (LDO) regulator with adaptively biased error amplifier for system-on-chip (SoC) core applications. The adaptive biasing technique increases both loop bandwidth and slew-rate of the LDO by 100% at full load condition without changing no-load quiescent current. Direct feedback to gate-to-source voltage of the NMOS regulation FET provides fast load transient response. The proposed LDO employs a cross-coupled common-gate (CG) input based error amplifier, with transconductance boosting, achieving twice unity-gain bandwidth in comparison to a typical folded-cascode common-source (CS) input stage. Low output impedance of NMOS regulation stage and low input impedance of the error amplifier reduce load dependent stability issue. The proposed regulator is designed and fabricated in a 0.18 lm CMOS technology with die-area of 0.21 mm2. The LDO generates a regulated output voltage of 1.4-1.6 V from an input voltage of 1.6-1.8 V, consumes 133 μ A quiescent current, and supports 0 pF to 50 pF load capacitance. Measured results show 166 mV undershoot with 19 ns settling time for a load step from 9 mA to 40 mA in 350 ps edge-time for zero-load capacitance. After using adaptive biasing, the settling time is reduced by 37% and 36% for 0 pF and 50 pF load, respectively.

Original languageEnglish (US)
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
StateAccepted/In press - May 30 2018


  • Adaptively biased error amplifier
  • cross-coupled common-gate input stage
  • fast load transient response
  • fast slew-rate.
  • NMOS low-dropout (LDO) regulator

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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