TY - JOUR
T1 - Adaptively Biased Output Cap-Less NMOS LDO with 19 ns Settling Time
AU - Mandal, Debashis
AU - Desai, Chirag
AU - Bakkaloglu, Bertan
AU - Kiaei, Sayfe
N1 - Funding Information:
Manuscript received March 11, 2018; revised April 29, 2018; accepted May 21, 2018. Date of publication May 31, 2018; date of current version January 29, 2019. This work was supported in part by NXP Semiconductors, Chandler, AZ, USA, and in part by the Connection One Center, Arizona State University, AZ, USA. This paper was recommended by Associate Editor J. Goes. (Debashis Mandal and Chirag Desai contributed equally to this work.) (Corresponding author: Debashis Mandal.) D. Mandal, B. Bakkaloglu, and S. Kiaei are with the School of Electrical, Computer, and Energy Engineering, Arizona State University, Tempe, AZ 85287 USA (e-mail: debashis.mandal@asu.edu).
Publisher Copyright:
© 2004-2012 IEEE.
PY - 2019
Y1 - 2019
N2 - This paper presents an output external capacitor-less, fully integrated, fast settling NMOS low-dropout (LDO) regulator with adaptively biased error amplifier (EA) for system-on-chip core applications. The adaptive biasing technique increases both loop bandwidth and slew-rate of the LDO by 100% at full load condition without changing no-load quiescent current. Direct feedback to gate-to-source voltage of the NMOS regulation FET provides fast load transient response. The proposed LDO employs a cross-coupled common-gate input based EA, with transconductance boosting, achieving twice unity-gain bandwidth in comparison to a typical folded-cascode common-source input stage. Low output impedance of NMOS regulation stage and low input impedance of the EA reduce load dependent stability issue. The proposed regulator is designed and fabricated in a 0.18-μm CMOS technology with die-area of 0.21 mm2. The LDO generates a regulated output voltage of 1.4-1.6 V from an input voltage of 1.6-1.8 V, consumes 133 μA quiescent current, and supports 0 pF to 50 pF load capacitance. Measured results show 166 mV undershoot with 19 ns settling time for a load step from 9 mA to 40 mA in 350 ps edge-time for zero-load capacitance. After using adaptive biasing, the settling time is reduced by 37% and 36% for 0 pF and 50 pF load, respectively.
AB - This paper presents an output external capacitor-less, fully integrated, fast settling NMOS low-dropout (LDO) regulator with adaptively biased error amplifier (EA) for system-on-chip core applications. The adaptive biasing technique increases both loop bandwidth and slew-rate of the LDO by 100% at full load condition without changing no-load quiescent current. Direct feedback to gate-to-source voltage of the NMOS regulation FET provides fast load transient response. The proposed LDO employs a cross-coupled common-gate input based EA, with transconductance boosting, achieving twice unity-gain bandwidth in comparison to a typical folded-cascode common-source input stage. Low output impedance of NMOS regulation stage and low input impedance of the EA reduce load dependent stability issue. The proposed regulator is designed and fabricated in a 0.18-μm CMOS technology with die-area of 0.21 mm2. The LDO generates a regulated output voltage of 1.4-1.6 V from an input voltage of 1.6-1.8 V, consumes 133 μA quiescent current, and supports 0 pF to 50 pF load capacitance. Measured results show 166 mV undershoot with 19 ns settling time for a load step from 9 mA to 40 mA in 350 ps edge-time for zero-load capacitance. After using adaptive biasing, the settling time is reduced by 37% and 36% for 0 pF and 50 pF load, respectively.
KW - Adaptively biased error amplifier
KW - NMOS lowdropout (LDO) regulator
KW - cross-coupled common-gate input stage
KW - fast load transient response
KW - fast slew-rate
UR - http://www.scopus.com/inward/record.url?scp=85047820875&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85047820875&partnerID=8YFLogxK
U2 - 10.1109/TCSII.2018.2842642
DO - 10.1109/TCSII.2018.2842642
M3 - Article
AN - SCOPUS:85047820875
SN - 1549-7747
VL - 66
SP - 167
EP - 171
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
IS - 2
M1 - 8370135
ER -