Abstract

This paper presents an output external capacitor-less, fully integrated, fast settling NMOS low-dropout (LDO) regulator with adaptively biased error amplifier for system-on-chip (SoC) core applications. The adaptive biasing technique increases both loop bandwidth and slew-rate of the LDO by 100% at full load condition without changing no-load quiescent current. Direct feedback to gate-to-source voltage of the NMOS regulation FET provides fast load transient response. The proposed LDO employs a cross-coupled common-gate (CG) input based error amplifier, with transconductance boosting, achieving twice unity-gain bandwidth in comparison to a typical folded-cascode common-source (CS) input stage. Low output impedance of NMOS regulation stage and low input impedance of the error amplifier reduce load dependent stability issue. The proposed regulator is designed and fabricated in a 0.18 lm CMOS technology with die-area of 0.21 mm2. The LDO generates a regulated output voltage of 1.4-1.6 V from an input voltage of 1.6-1.8 V, consumes 133 μ A quiescent current, and supports 0 pF to 50 pF load capacitance. Measured results show 166 mV undershoot with 19 ns settling time for a load step from 9 mA to 40 mA in 350 ps edge-time for zero-load capacitance. After using adaptive biasing, the settling time is reduced by 37% and 36% for 0 pF and 50 pF load, respectively.

Original languageEnglish (US)
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
DOIs
StateAccepted/In press - May 30 2018

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Electric potential
Capacitance
Bandwidth
Transconductance
Field effect transistors
Transient analysis
Capacitors
Feedback
System-on-chip

Keywords

  • Adaptively biased error amplifier
  • cross-coupled common-gate input stage
  • fast load transient response
  • fast slew-rate.
  • NMOS low-dropout (LDO) regulator

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

@article{77f8520d5ba242b9952ba639294afb66,
title = "Adaptively Biased Output Cap-Less NMOS LDO with 19 ns Settling-Time",
abstract = "This paper presents an output external capacitor-less, fully integrated, fast settling NMOS low-dropout (LDO) regulator with adaptively biased error amplifier for system-on-chip (SoC) core applications. The adaptive biasing technique increases both loop bandwidth and slew-rate of the LDO by 100{\%} at full load condition without changing no-load quiescent current. Direct feedback to gate-to-source voltage of the NMOS regulation FET provides fast load transient response. The proposed LDO employs a cross-coupled common-gate (CG) input based error amplifier, with transconductance boosting, achieving twice unity-gain bandwidth in comparison to a typical folded-cascode common-source (CS) input stage. Low output impedance of NMOS regulation stage and low input impedance of the error amplifier reduce load dependent stability issue. The proposed regulator is designed and fabricated in a 0.18 lm CMOS technology with die-area of 0.21 mm2. The LDO generates a regulated output voltage of 1.4-1.6 V from an input voltage of 1.6-1.8 V, consumes 133 μ A quiescent current, and supports 0 pF to 50 pF load capacitance. Measured results show 166 mV undershoot with 19 ns settling time for a load step from 9 mA to 40 mA in 350 ps edge-time for zero-load capacitance. After using adaptive biasing, the settling time is reduced by 37{\%} and 36{\%} for 0 pF and 50 pF load, respectively.",
keywords = "Adaptively biased error amplifier, cross-coupled common-gate input stage, fast load transient response, fast slew-rate., NMOS low-dropout (LDO) regulator",
author = "Debashis Mandal and Chirag Desai and Bertan Bakkaloglu and Sayfe Kiaei",
year = "2018",
month = "5",
day = "30",
doi = "10.1109/TCSII.2018.2842642",
language = "English (US)",
journal = "IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing",
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T1 - Adaptively Biased Output Cap-Less NMOS LDO with 19 ns Settling-Time

AU - Mandal, Debashis

AU - Desai, Chirag

AU - Bakkaloglu, Bertan

AU - Kiaei, Sayfe

PY - 2018/5/30

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N2 - This paper presents an output external capacitor-less, fully integrated, fast settling NMOS low-dropout (LDO) regulator with adaptively biased error amplifier for system-on-chip (SoC) core applications. The adaptive biasing technique increases both loop bandwidth and slew-rate of the LDO by 100% at full load condition without changing no-load quiescent current. Direct feedback to gate-to-source voltage of the NMOS regulation FET provides fast load transient response. The proposed LDO employs a cross-coupled common-gate (CG) input based error amplifier, with transconductance boosting, achieving twice unity-gain bandwidth in comparison to a typical folded-cascode common-source (CS) input stage. Low output impedance of NMOS regulation stage and low input impedance of the error amplifier reduce load dependent stability issue. The proposed regulator is designed and fabricated in a 0.18 lm CMOS technology with die-area of 0.21 mm2. The LDO generates a regulated output voltage of 1.4-1.6 V from an input voltage of 1.6-1.8 V, consumes 133 μ A quiescent current, and supports 0 pF to 50 pF load capacitance. Measured results show 166 mV undershoot with 19 ns settling time for a load step from 9 mA to 40 mA in 350 ps edge-time for zero-load capacitance. After using adaptive biasing, the settling time is reduced by 37% and 36% for 0 pF and 50 pF load, respectively.

AB - This paper presents an output external capacitor-less, fully integrated, fast settling NMOS low-dropout (LDO) regulator with adaptively biased error amplifier for system-on-chip (SoC) core applications. The adaptive biasing technique increases both loop bandwidth and slew-rate of the LDO by 100% at full load condition without changing no-load quiescent current. Direct feedback to gate-to-source voltage of the NMOS regulation FET provides fast load transient response. The proposed LDO employs a cross-coupled common-gate (CG) input based error amplifier, with transconductance boosting, achieving twice unity-gain bandwidth in comparison to a typical folded-cascode common-source (CS) input stage. Low output impedance of NMOS regulation stage and low input impedance of the error amplifier reduce load dependent stability issue. The proposed regulator is designed and fabricated in a 0.18 lm CMOS technology with die-area of 0.21 mm2. The LDO generates a regulated output voltage of 1.4-1.6 V from an input voltage of 1.6-1.8 V, consumes 133 μ A quiescent current, and supports 0 pF to 50 pF load capacitance. Measured results show 166 mV undershoot with 19 ns settling time for a load step from 9 mA to 40 mA in 350 ps edge-time for zero-load capacitance. After using adaptive biasing, the settling time is reduced by 37% and 36% for 0 pF and 50 pF load, respectively.

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