A robust alternate repeater technique for high performance busses in the multi-core era

Himanshu Kaul, Jae-sun Seo, Mark Anders, Dennis Sylvester, Ram Krishnamurthy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

This paper describes an alternate repeater insertion technique that uses correct-by-construction polarities to reduce worst-case miller coupling factor (MCF) across any multiple segmented portion of a repeated bus. Simple static CMOS circuits with nominal p-n skews allow drop-in replacement while maintaining robust operation. For the same repeater area, number and position of repeaters of conventional busses, this technique simultaneously reduces delay by 15%, energy by 29% and peak current by 12% for 2-8mm on-chip busses in 1.2V, 65nm CMOS. Under equal delay constraints, the proposed technique reduces worst-case energy and peak current by 39% and 36%, respectively. The technique easily extends to shared busses for multi-core designs and shows a 41% improvement in energy-efficiency for a 10mm 5GHz multi-cycle on-chip core-tocore bus.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
Pages372-375
Number of pages4
DOIs
StatePublished - 2008
Externally publishedYes
Event2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 - Seattle, WA, United States
Duration: May 18 2008May 21 2008

Other

Other2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
CountryUnited States
CitySeattle, WA
Period5/18/085/21/08

Fingerprint

Telecommunication repeaters
Energy efficiency
Networks (circuits)

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Kaul, H., Seo, J., Anders, M., Sylvester, D., & Krishnamurthy, R. (2008). A robust alternate repeater technique for high performance busses in the multi-core era. In Proceedings - IEEE International Symposium on Circuits and Systems (pp. 372-375). [4541432] https://doi.org/10.1109/ISCAS.2008.4541432

A robust alternate repeater technique for high performance busses in the multi-core era. / Kaul, Himanshu; Seo, Jae-sun; Anders, Mark; Sylvester, Dennis; Krishnamurthy, Ram.

Proceedings - IEEE International Symposium on Circuits and Systems. 2008. p. 372-375 4541432.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kaul, H, Seo, J, Anders, M, Sylvester, D & Krishnamurthy, R 2008, A robust alternate repeater technique for high performance busses in the multi-core era. in Proceedings - IEEE International Symposium on Circuits and Systems., 4541432, pp. 372-375, 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008, Seattle, WA, United States, 5/18/08. https://doi.org/10.1109/ISCAS.2008.4541432
Kaul H, Seo J, Anders M, Sylvester D, Krishnamurthy R. A robust alternate repeater technique for high performance busses in the multi-core era. In Proceedings - IEEE International Symposium on Circuits and Systems. 2008. p. 372-375. 4541432 https://doi.org/10.1109/ISCAS.2008.4541432
Kaul, Himanshu ; Seo, Jae-sun ; Anders, Mark ; Sylvester, Dennis ; Krishnamurthy, Ram. / A robust alternate repeater technique for high performance busses in the multi-core era. Proceedings - IEEE International Symposium on Circuits and Systems. 2008. pp. 372-375
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