A robust alternate repeater technique for high performance busses in the multi-core era

Himanshu Kaul, Jae Sun Seo, Mark Anders, Dennis Sylvester, Ram Krishnamurthy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations

Abstract

This paper describes an alternate repeater insertion technique that uses correct-by-construction polarities to reduce worst-case miller coupling factor (MCF) across any multiple segmented portion of a repeated bus. Simple static CMOS circuits with nominal p-n skews allow drop-in replacement while maintaining robust operation. For the same repeater area, number and position of repeaters of conventional busses, this technique simultaneously reduces delay by 15%, energy by 29% and peak current by 12% for 2-8mm on-chip busses in 1.2V, 65nm CMOS. Under equal delay constraints, the proposed technique reduces worst-case energy and peak current by 39% and 36%, respectively. The technique easily extends to shared busses for multi-core designs and shows a 41% improvement in energy-efficiency for a 10mm 5GHz multi-cycle on-chip core-tocore bus.

Original languageEnglish (US)
Title of host publication2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
Pages372-375
Number of pages4
DOIs
StatePublished - Sep 19 2008
Externally publishedYes
Event2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 - Seattle, WA, United States
Duration: May 18 2008May 21 2008

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Other

Other2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
CountryUnited States
CitySeattle, WA
Period5/18/085/21/08

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A robust alternate repeater technique for high performance busses in the multi-core era'. Together they form a unique fingerprint.

  • Cite this

    Kaul, H., Seo, J. S., Anders, M., Sylvester, D., & Krishnamurthy, R. (2008). A robust alternate repeater technique for high performance busses in the multi-core era. In 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 (pp. 372-375). [4541432] (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2008.4541432