6 Scopus citations

Abstract

A radix-3, 4-trits, Ternary Successive Approximation Analog to Digital Converter (TSAR-ADC), with an option to extend to radix-N approaches is presented. Proposed TSAR-ADC architecture generates 4 ternary outputs spanning 34=81 binary levels linearly for a rail-to-rail input voltage ranging from 0 to 3.3V. The radix-3 TSAR-ADC takes only 4 clock cycles for producing 4-trits or 6.33 bits in comparison to 7 clock cycles in a conventional binary SAR converter. The ADC is designed and fabricated on a 0.35μm double poly, three level metal CMOS technology, achieving less than 1 LSB INL, 0.8 LSB of DNL, consuming 1.6-mW from a 3.3-V supply.

Original languageEnglish (US)
Title of host publicationISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
Subtitle of host publicationNano-Bio Circuit Fabrics and Systems
Pages1460-1463
Number of pages4
DOIs
StatePublished - Aug 31 2010
Event2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France
Duration: May 30 2010Jun 2 2010

Publication series

NameISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Other

Other2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
CountryFrance
CityParis
Period5/30/106/2/10

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A radix-3 SAR analog-to-digital converter'. Together they form a unique fingerprint.

Cite this