TY - GEN
T1 - A parallel stochastic computing system with improved accuracy
AU - Miao, Lifeng
AU - Chakrabarti, Chaitali
PY - 2013/1/1
Y1 - 2013/1/1
N2 - Stochastic computing (SC) is an attractive computing paradigm because of its fault tolerance and hardware efficiency. Unfortunately, existing SC systems suffer from large latency and inaccuracy problems. In this paper, we propose a new parallel stochastic computing (PSC) system which has higher computing accuracy and faster processing speed compared to existing SC systems. It uses the nibble serial data organization to reduce the latency and a combination of memory based weighted binary generator and data shuffling to improve the accuracy. Simulations on finite impulse response (FIR) filters show that the proposed system with 4 nibbles achieves 35% improvement in accuracy with about 3.5 times increase in processing speed compared to traditional SC. Like SC systems, PSC is also more tolerant of soft errors compared to conventional 2's complement implementations. For a 4-tap FIR filter a 10% injected error causes the root-meansquare- error (RMSE) of PSC to be 0.053 compared to RMSE of 0.188 for 2's complement implementation.
AB - Stochastic computing (SC) is an attractive computing paradigm because of its fault tolerance and hardware efficiency. Unfortunately, existing SC systems suffer from large latency and inaccuracy problems. In this paper, we propose a new parallel stochastic computing (PSC) system which has higher computing accuracy and faster processing speed compared to existing SC systems. It uses the nibble serial data organization to reduce the latency and a combination of memory based weighted binary generator and data shuffling to improve the accuracy. Simulations on finite impulse response (FIR) filters show that the proposed system with 4 nibbles achieves 35% improvement in accuracy with about 3.5 times increase in processing speed compared to traditional SC. Like SC systems, PSC is also more tolerant of soft errors compared to conventional 2's complement implementations. For a 4-tap FIR filter a 10% injected error causes the root-meansquare- error (RMSE) of PSC to be 0.053 compared to RMSE of 0.188 for 2's complement implementation.
KW - FIR filter
KW - FPGA
KW - Nibble serial
KW - Parallel architecture
KW - Stochastic computing
UR - http://www.scopus.com/inward/record.url?scp=84896455084&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84896455084&partnerID=8YFLogxK
U2 - 10.1109/sips.2013.6674504
DO - 10.1109/sips.2013.6674504
M3 - Conference contribution
AN - SCOPUS:84896455084
SN - 9781467362382
T3 - IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
SP - 195
EP - 200
BT - 2013 IEEE Workshop on Signal Processing Systems, SiPS 2013
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2013 IEEE Workshop on Signal Processing Systems, SiPS 2013
Y2 - 16 October 2013 through 18 October 2013
ER -