8 Citations (Scopus)

Abstract

Stochastic computing (SC) is an attractive computing paradigm because of its fault tolerance and hardware efficiency. Unfortunately, existing SC systems suffer from large latency and inaccuracy problems. In this paper, we propose a new parallel stochastic computing (PSC) system which has higher computing accuracy and faster processing speed compared to existing SC systems. It uses the nibble serial data organization to reduce the latency and a combination of memory based weighted binary generator and data shuffling to improve the accuracy. Simulations on finite impulse response (FIR) filters show that the proposed system with 4 nibbles achieves 35% improvement in accuracy with about 3.5 times increase in processing speed compared to traditional SC. Like SC systems, PSC is also more tolerant of soft errors compared to conventional 2's complement implementations. For a 4-tap FIR filter a 10% injected error causes the root-meansquare- error (RMSE) of PSC to be 0.053 compared to RMSE of 0.188 for 2's complement implementation.

Original languageEnglish (US)
Title of host publicationIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages195-200
Number of pages6
ISBN (Print)9781467362382
StatePublished - 2013
Event2013 IEEE Workshop on Signal Processing Systems, SiPS 2013 - Taipei, Taiwan, Province of China
Duration: Oct 16 2013Oct 18 2013

Other

Other2013 IEEE Workshop on Signal Processing Systems, SiPS 2013
CountryTaiwan, Province of China
CityTaipei
Period10/16/1310/18/13

Fingerprint

Computing
FIR filters
Processing
Fault tolerance
Impulse Response
Latency
Hardware
Data storage equipment
Complement
Roots
Filter
Soft Error
Parallel Systems
Fault Tolerance
Paradigm
Generator
Binary
Simulation

Keywords

  • FIR filter
  • FPGA
  • Nibble serial
  • Parallel architecture
  • Stochastic computing

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Signal Processing
  • Applied Mathematics
  • Hardware and Architecture

Cite this

Miao, L., & Chakrabarti, C. (2013). A parallel stochastic computing system with improved accuracy. In IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation (pp. 195-200). [6674504] Institute of Electrical and Electronics Engineers Inc..

A parallel stochastic computing system with improved accuracy. / Miao, Lifeng; Chakrabarti, Chaitali.

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation. Institute of Electrical and Electronics Engineers Inc., 2013. p. 195-200 6674504.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Miao, L & Chakrabarti, C 2013, A parallel stochastic computing system with improved accuracy. in IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation., 6674504, Institute of Electrical and Electronics Engineers Inc., pp. 195-200, 2013 IEEE Workshop on Signal Processing Systems, SiPS 2013, Taipei, Taiwan, Province of China, 10/16/13.
Miao L, Chakrabarti C. A parallel stochastic computing system with improved accuracy. In IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation. Institute of Electrical and Electronics Engineers Inc. 2013. p. 195-200. 6674504
Miao, Lifeng ; Chakrabarti, Chaitali. / A parallel stochastic computing system with improved accuracy. IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation. Institute of Electrical and Electronics Engineers Inc., 2013. pp. 195-200
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