A modified shifting bottleneck heuristic for minimizing total weighted tardiness in complex job shops

Scott J. Mason, John Fowler, W. Matthew Carlyle

Research output: Contribution to journalArticle

145 Scopus citations

Abstract

Increases in the demand for integrated circuits have highlighted the importance of meeting customer quality and on-time delivery expectations in the semiconductor industry. A modified shifting bottleneck heuristic is developed for minimizing the total weighted tardiness in a semiconductor wafer fabrication facility. This 'complex' job shop is characterized by re-entrant or re-circulating product flow through a number of different tool groups (one or more machines operating in parallel). These tool groups typically contain batching machines, as well as machines that are subject to sequence-dependent setups. The disjunctive graph of the complex job shop is presented, along with a description of the proposed heuristic. Preliminary results indicate the heuristic's potential for promoting on-time deliveries by semiconductor manufacturers for their customers' orders.

Original languageEnglish (US)
Pages (from-to)247-262
Number of pages16
JournalJournal of Scheduling
Volume5
Issue number3
DOIs
StatePublished - Dec 1 2002

Keywords

  • Job shop
  • Semiconductor
  • Shifting bottleneck
  • Weighted tardiness

ASJC Scopus subject areas

  • Software
  • Engineering(all)
  • Management Science and Operations Research
  • Artificial Intelligence

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