TY - GEN
T1 - A method for generating structurally aligned high quality grids and its application to the simulation of a trench gate MOSFET
AU - Heitzinger, Clemens
AU - Sheikholeslami, Alireza
AU - Park, Jong Mun
AU - Selberherr, Siegfried
N1 - Publisher Copyright:
© 2003 IEEE.
PY - 2003
Y1 - 2003
N2 - The error of the numeric approximation of the semiconductor device equations particularly depends on the grid used for the discretization. Since the most interesting regions of the device are generally straightforward to identify, the method of choice is to use structurally aligned grids. Here, we present an algorithm for generating structurally aligned grids, including anisotropy, and for producing grids whose resolution varies over several orders of magnitude. Furthermore, the areas with increased resolution and the corresponding resolutions can be defined in a flexible manner and criteria on grid quality can be enforced. The grid generation algorithm was applied to sample structures which highlight the features of this method. Furthermore we generated grids for the simulation of a high voltage trench gate MOSFET. In order to resolve the junction regions accurately, four regions were defined where the grid was grown in several directions with varying resolutions. Finally device simulations performed by MINIMOS NT show current voltage characteristics and the threshold voltage.
AB - The error of the numeric approximation of the semiconductor device equations particularly depends on the grid used for the discretization. Since the most interesting regions of the device are generally straightforward to identify, the method of choice is to use structurally aligned grids. Here, we present an algorithm for generating structurally aligned grids, including anisotropy, and for producing grids whose resolution varies over several orders of magnitude. Furthermore, the areas with increased resolution and the corresponding resolutions can be defined in a flexible manner and criteria on grid quality can be enforced. The grid generation algorithm was applied to sample structures which highlight the features of this method. Furthermore we generated grids for the simulation of a high voltage trench gate MOSFET. In order to resolve the junction regions accurately, four regions were defined where the grid was grown in several directions with varying resolutions. Finally device simulations performed by MINIMOS NT show current voltage characteristics and the threshold voltage.
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U2 - 10.1109/ESSDERC.2003.1256912
DO - 10.1109/ESSDERC.2003.1256912
M3 - Conference contribution
AN - SCOPUS:84907707900
SN - 9780780379992
T3 - European Solid-State Device Research Conference
SP - 457
EP - 460
BT - ESSDERC 2003 - Proceedings of the 33rd European Solid-State Device Research Conference
A2 - Franca, Jose
A2 - Freitas, Paulo
PB - IEEE Computer Society
T2 - 33rd European Solid-State Device Research Conference, ESSDERC 2003
Y2 - 16 September 2003 through 18 September 2003
ER -