A method for generating structurally aligned high quality grids and its application to the simulation of a trench gate MOSFET

Clemens Heitzinger, Alireza Sheikholeslami, Jong Mun Park, Siegfried Selberherr

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The error of the numeric approximation of the semiconductor device equations particularly depends on the grid used for the discretization. Since the most interesting regions of the device are generally straightforward to identify, the method of choice is to use structurally aligned grids. Here, we present an algorithm for generating structurally aligned grids, including anisotropy, and for producing grids whose resolution varies over several orders of magnitude. Furthermore, the areas with increased resolution and the corresponding resolutions can be defined in a flexible manner and criteria on grid quality can be enforced. The grid generation algorithm was applied to sample structures which highlight the features of this method. Furthermore we generated grids for the simulation of a high voltage trench gate MOSFET. In order to resolve the junction regions accurately, four regions were defined where the grid was grown in several directions with varying resolutions. Finally device simulations performed by MINIMOS NT show current voltage characteristics and the threshold voltage.

Original languageEnglish (US)
Title of host publicationEuropean Solid-State Device Research Conference
PublisherIEEE Computer Society
Pages457-460
Number of pages4
ISBN (Print)0780379993, 9780780379992
DOIs
StatePublished - 2003
Externally publishedYes
Event33rd European Solid-State Device Research Conference, ESSDERC 2003 - Estoril, Portugal
Duration: Sep 16 2003Sep 18 2003

Other

Other33rd European Solid-State Device Research Conference, ESSDERC 2003
CountryPortugal
CityEstoril
Period9/16/039/18/03

Fingerprint

Current voltage characteristics
Semiconductor devices
Threshold voltage
Anisotropy
Electric potential

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

Cite this

Heitzinger, C., Sheikholeslami, A., Park, J. M., & Selberherr, S. (2003). A method for generating structurally aligned high quality grids and its application to the simulation of a trench gate MOSFET. In European Solid-State Device Research Conference (pp. 457-460). [1256912] IEEE Computer Society. https://doi.org/10.1109/ESSDERC.2003.1256912

A method for generating structurally aligned high quality grids and its application to the simulation of a trench gate MOSFET. / Heitzinger, Clemens; Sheikholeslami, Alireza; Park, Jong Mun; Selberherr, Siegfried.

European Solid-State Device Research Conference. IEEE Computer Society, 2003. p. 457-460 1256912.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Heitzinger, C, Sheikholeslami, A, Park, JM & Selberherr, S 2003, A method for generating structurally aligned high quality grids and its application to the simulation of a trench gate MOSFET. in European Solid-State Device Research Conference., 1256912, IEEE Computer Society, pp. 457-460, 33rd European Solid-State Device Research Conference, ESSDERC 2003, Estoril, Portugal, 9/16/03. https://doi.org/10.1109/ESSDERC.2003.1256912
Heitzinger C, Sheikholeslami A, Park JM, Selberherr S. A method for generating structurally aligned high quality grids and its application to the simulation of a trench gate MOSFET. In European Solid-State Device Research Conference. IEEE Computer Society. 2003. p. 457-460. 1256912 https://doi.org/10.1109/ESSDERC.2003.1256912
Heitzinger, Clemens ; Sheikholeslami, Alireza ; Park, Jong Mun ; Selberherr, Siegfried. / A method for generating structurally aligned high quality grids and its application to the simulation of a trench gate MOSFET. European Solid-State Device Research Conference. IEEE Computer Society, 2003. pp. 457-460
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