### Abstract

This paper presents resource and latency constrained scheduling algorithms to minimize power/energy consumption when the resources operate at multiple voltages (5 V, 3.3 V, 2.4 V, and 1.5 V). The proposed algorithms are based on efficient distribution of slack among the nodes in the data-flow graph. The distribution procedure tries to implement the minimum energy relation derived using the Lagrange multiplier method in an iterative fashion. Two algorithms are proposed, 1) a low complexity O(n ^{2}) algorithm and 2) a high complexity O(n ^{2} log(L)) algorithm, where n is the number of nodes and L is the latency. Experiments with some HLS benchmark examples show that the proposed algorithms achieve significant power/energy reduction. For instance, when the latency constraint is 1.5 times the critical path delay, the average reduction is 39%.

Original language | English (US) |
---|---|

Pages (from-to) | 6-14 |

Number of pages | 9 |

Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |

Volume | 10 |

Issue number | 1 |

DOIs | |

State | Published - Feb 2002 |

### Fingerprint

### Keywords

- Allocation
- Data-flow graph
- Lagrange multiplier method
- Low power
- Multiple voltages
- Resource and latency constraint
- Scheduling

### ASJC Scopus subject areas

- Electrical and Electronic Engineering
- Hardware and Architecture

### Cite this

**A low power scheduling scheme with resources operating at multiple voltages.** / Manzak, Ali; Chakrabarti, Chaitali.

Research output: Contribution to journal › Article

*IEEE Transactions on Very Large Scale Integration (VLSI) Systems*, vol. 10, no. 1, pp. 6-14. https://doi.org/10.1109/92.988725

}

TY - JOUR

T1 - A low power scheduling scheme with resources operating at multiple voltages

AU - Manzak, Ali

AU - Chakrabarti, Chaitali

PY - 2002/2

Y1 - 2002/2

N2 - This paper presents resource and latency constrained scheduling algorithms to minimize power/energy consumption when the resources operate at multiple voltages (5 V, 3.3 V, 2.4 V, and 1.5 V). The proposed algorithms are based on efficient distribution of slack among the nodes in the data-flow graph. The distribution procedure tries to implement the minimum energy relation derived using the Lagrange multiplier method in an iterative fashion. Two algorithms are proposed, 1) a low complexity O(n 2) algorithm and 2) a high complexity O(n 2 log(L)) algorithm, where n is the number of nodes and L is the latency. Experiments with some HLS benchmark examples show that the proposed algorithms achieve significant power/energy reduction. For instance, when the latency constraint is 1.5 times the critical path delay, the average reduction is 39%.

AB - This paper presents resource and latency constrained scheduling algorithms to minimize power/energy consumption when the resources operate at multiple voltages (5 V, 3.3 V, 2.4 V, and 1.5 V). The proposed algorithms are based on efficient distribution of slack among the nodes in the data-flow graph. The distribution procedure tries to implement the minimum energy relation derived using the Lagrange multiplier method in an iterative fashion. Two algorithms are proposed, 1) a low complexity O(n 2) algorithm and 2) a high complexity O(n 2 log(L)) algorithm, where n is the number of nodes and L is the latency. Experiments with some HLS benchmark examples show that the proposed algorithms achieve significant power/energy reduction. For instance, when the latency constraint is 1.5 times the critical path delay, the average reduction is 39%.

KW - Allocation

KW - Data-flow graph

KW - Lagrange multiplier method

KW - Low power

KW - Multiple voltages

KW - Resource and latency constraint

KW - Scheduling

UR - http://www.scopus.com/inward/record.url?scp=0036477148&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0036477148&partnerID=8YFLogxK

U2 - 10.1109/92.988725

DO - 10.1109/92.988725

M3 - Article

AN - SCOPUS:0036477148

VL - 10

SP - 6

EP - 14

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 1

ER -