A low power scheduling scheme with resources operating at multiple voltages

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72 Citations (Scopus)

Abstract

This paper presents resource and latency constrained scheduling algorithms to minimize power/energy consumption when the resources operate at multiple voltages (5 V, 3.3 V, 2.4 V, and 1.5 V). The proposed algorithms are based on efficient distribution of slack among the nodes in the data-flow graph. The distribution procedure tries to implement the minimum energy relation derived using the Lagrange multiplier method in an iterative fashion. Two algorithms are proposed, 1) a low complexity O(n 2) algorithm and 2) a high complexity O(n 2 log(L)) algorithm, where n is the number of nodes and L is the latency. Experiments with some HLS benchmark examples show that the proposed algorithms achieve significant power/energy reduction. For instance, when the latency constraint is 1.5 times the critical path delay, the average reduction is 39%.

Original languageEnglish (US)
Pages (from-to)6-14
Number of pages9
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume10
Issue number1
DOIs
StatePublished - Feb 2002

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Scheduling
Electric potential
Data flow graphs
Lagrange multipliers
Scheduling algorithms
Energy utilization
Experiments

Keywords

  • Allocation
  • Data-flow graph
  • Lagrange multiplier method
  • Low power
  • Multiple voltages
  • Resource and latency constraint
  • Scheduling

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

Cite this

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title = "A low power scheduling scheme with resources operating at multiple voltages",
abstract = "This paper presents resource and latency constrained scheduling algorithms to minimize power/energy consumption when the resources operate at multiple voltages (5 V, 3.3 V, 2.4 V, and 1.5 V). The proposed algorithms are based on efficient distribution of slack among the nodes in the data-flow graph. The distribution procedure tries to implement the minimum energy relation derived using the Lagrange multiplier method in an iterative fashion. Two algorithms are proposed, 1) a low complexity O(n 2) algorithm and 2) a high complexity O(n 2 log(L)) algorithm, where n is the number of nodes and L is the latency. Experiments with some HLS benchmark examples show that the proposed algorithms achieve significant power/energy reduction. For instance, when the latency constraint is 1.5 times the critical path delay, the average reduction is 39{\%}.",
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