A low-power double-edge-triggered address pointer circuit for FIFO memory design

Saravanan Ramamoorthy, Haibo Wang, Sarma Vrudhula

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a novel design of address pointer for FIFO memory circuits. Advantages of the proposed design include: reduced capacitive load on the pointer clock path, the use of a true single-phase clock, and double-edge-triggering clock scheme. The circuit has low power consumption, is immune to circuit racing conditions and suitable for high-speed operations. Techniques to implement clock gating in pointer circuit design for further reducing power consumption are also discussed. The proposed circuit is implemented with a 65nm CMOS technology and its performance is compared with previous pointer circuits.

Original languageEnglish (US)
Title of host publicationProceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008
Pages123-126
Number of pages4
DOIs
StatePublished - Aug 25 2008
Event9th International Symposium on Quality Electronic Design, ISQED 2008 - San Jose, CA, United States
Duration: Mar 17 2008Mar 19 2008

Publication series

NameProceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008

Other

Other9th International Symposium on Quality Electronic Design, ISQED 2008
CountryUnited States
CitySan Jose, CA
Period3/17/083/19/08

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Ramamoorthy, S., Wang, H., & Vrudhula, S. (2008). A low-power double-edge-triggered address pointer circuit for FIFO memory design. In Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008 (pp. 123-126). [4479711] (Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008). https://doi.org/10.1109/ISQED.2008.4479711