A high-level modeling and simulation approach using test-driven cellular automata for fast performance analysis of RTL NoC designs

Moon Gi Seok, Hessam Sarjoughian, Daejin Park

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    The simulation speedup of designed RTL NoC regarding the packet transmission is essential to analyze the performance or to optimize NoC parameters for various combinations of intellectual-property (IP) blocks, which requires repeated computations for parameter-space exploration. In this paper, we propose a high-level modeling and simulation (M&S) approach using a revised cellular automata (CA) concept to speed up simulation of dynamic flit movements and queue occupancy within target RTL NoC. The CA abstracts the detailed RTL operations with the view of deciding a cell's state of actions (related to moving packet flits and changing the connection between CA cells) using its own high-level states and those of neighbors, and executing relevant operations to the decided action states. During the performing the operations including connection requests and acceptances, architecture-independent and user-developed routing and arbitration functions are utilized. The decision regarding the action states follows a rule set, which is generated by the proposed test environment. The proposed method was applied to an open-source Verilog NoC, which achieves simulation speedup by approximately 8 to 31 times for a given parameter set.

    Original languageEnglish (US)
    Title of host publicationASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages420-425
    Number of pages6
    ISBN (Electronic)9781450360074
    DOIs
    StatePublished - Jan 21 2019
    Event24th Asia and South Pacific Design Automation Conference, ASPDAC 2019 - Tokyo, Japan
    Duration: Jan 21 2019Jan 24 2019

    Other

    Other24th Asia and South Pacific Design Automation Conference, ASPDAC 2019
    CountryJapan
    CityTokyo
    Period1/21/191/24/19

    Fingerprint

    Cellular automata
    Computer hardware description languages
    Network-on-chip

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Computer Science Applications
    • Computer Graphics and Computer-Aided Design

    Cite this

    Gi Seok, M., Sarjoughian, H., & Park, D. (2019). A high-level modeling and simulation approach using test-driven cellular automata for fast performance analysis of RTL NoC designs. In ASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference (pp. 420-425). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/3287624.3287648

    A high-level modeling and simulation approach using test-driven cellular automata for fast performance analysis of RTL NoC designs. / Gi Seok, Moon; Sarjoughian, Hessam; Park, Daejin.

    ASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc., 2019. p. 420-425.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Gi Seok, M, Sarjoughian, H & Park, D 2019, A high-level modeling and simulation approach using test-driven cellular automata for fast performance analysis of RTL NoC designs. in ASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc., pp. 420-425, 24th Asia and South Pacific Design Automation Conference, ASPDAC 2019, Tokyo, Japan, 1/21/19. https://doi.org/10.1145/3287624.3287648
    Gi Seok M, Sarjoughian H, Park D. A high-level modeling and simulation approach using test-driven cellular automata for fast performance analysis of RTL NoC designs. In ASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc. 2019. p. 420-425 https://doi.org/10.1145/3287624.3287648
    Gi Seok, Moon ; Sarjoughian, Hessam ; Park, Daejin. / A high-level modeling and simulation approach using test-driven cellular automata for fast performance analysis of RTL NoC designs. ASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 420-425
    @inproceedings{c151e8e422474984b29b816ad2c30c97,
    title = "A high-level modeling and simulation approach using test-driven cellular automata for fast performance analysis of RTL NoC designs",
    abstract = "The simulation speedup of designed RTL NoC regarding the packet transmission is essential to analyze the performance or to optimize NoC parameters for various combinations of intellectual-property (IP) blocks, which requires repeated computations for parameter-space exploration. In this paper, we propose a high-level modeling and simulation (M&S) approach using a revised cellular automata (CA) concept to speed up simulation of dynamic flit movements and queue occupancy within target RTL NoC. The CA abstracts the detailed RTL operations with the view of deciding a cell's state of actions (related to moving packet flits and changing the connection between CA cells) using its own high-level states and those of neighbors, and executing relevant operations to the decided action states. During the performing the operations including connection requests and acceptances, architecture-independent and user-developed routing and arbitration functions are utilized. The decision regarding the action states follows a rule set, which is generated by the proposed test environment. The proposed method was applied to an open-source Verilog NoC, which achieves simulation speedup by approximately 8 to 31 times for a given parameter set.",
    author = "{Gi Seok}, Moon and Hessam Sarjoughian and Daejin Park",
    year = "2019",
    month = "1",
    day = "21",
    doi = "10.1145/3287624.3287648",
    language = "English (US)",
    pages = "420--425",
    booktitle = "ASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference",
    publisher = "Institute of Electrical and Electronics Engineers Inc.",

    }

    TY - GEN

    T1 - A high-level modeling and simulation approach using test-driven cellular automata for fast performance analysis of RTL NoC designs

    AU - Gi Seok, Moon

    AU - Sarjoughian, Hessam

    AU - Park, Daejin

    PY - 2019/1/21

    Y1 - 2019/1/21

    N2 - The simulation speedup of designed RTL NoC regarding the packet transmission is essential to analyze the performance or to optimize NoC parameters for various combinations of intellectual-property (IP) blocks, which requires repeated computations for parameter-space exploration. In this paper, we propose a high-level modeling and simulation (M&S) approach using a revised cellular automata (CA) concept to speed up simulation of dynamic flit movements and queue occupancy within target RTL NoC. The CA abstracts the detailed RTL operations with the view of deciding a cell's state of actions (related to moving packet flits and changing the connection between CA cells) using its own high-level states and those of neighbors, and executing relevant operations to the decided action states. During the performing the operations including connection requests and acceptances, architecture-independent and user-developed routing and arbitration functions are utilized. The decision regarding the action states follows a rule set, which is generated by the proposed test environment. The proposed method was applied to an open-source Verilog NoC, which achieves simulation speedup by approximately 8 to 31 times for a given parameter set.

    AB - The simulation speedup of designed RTL NoC regarding the packet transmission is essential to analyze the performance or to optimize NoC parameters for various combinations of intellectual-property (IP) blocks, which requires repeated computations for parameter-space exploration. In this paper, we propose a high-level modeling and simulation (M&S) approach using a revised cellular automata (CA) concept to speed up simulation of dynamic flit movements and queue occupancy within target RTL NoC. The CA abstracts the detailed RTL operations with the view of deciding a cell's state of actions (related to moving packet flits and changing the connection between CA cells) using its own high-level states and those of neighbors, and executing relevant operations to the decided action states. During the performing the operations including connection requests and acceptances, architecture-independent and user-developed routing and arbitration functions are utilized. The decision regarding the action states follows a rule set, which is generated by the proposed test environment. The proposed method was applied to an open-source Verilog NoC, which achieves simulation speedup by approximately 8 to 31 times for a given parameter set.

    UR - http://www.scopus.com/inward/record.url?scp=85061112323&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=85061112323&partnerID=8YFLogxK

    U2 - 10.1145/3287624.3287648

    DO - 10.1145/3287624.3287648

    M3 - Conference contribution

    SP - 420

    EP - 425

    BT - ASP-DAC 2019 - 24th Asia and South Pacific Design Automation Conference

    PB - Institute of Electrical and Electronics Engineers Inc.

    ER -