TY - GEN
T1 - A flexible design methodology for analog test wrappers in mixed-signal SOCs
AU - Sehgal, Anuja
AU - Ozev, Sule
AU - Chakrabarty, Krishnendu
PY - 2005
Y1 - 2005
N2 - The manufacturing test cost for mixed-signal SOCs is widely recognized to be much higher than that for digital SOCs. It has been shown in recent prior work that the use of analog test wrappers (ATWs) for embedded analog cores in mixed-signal. SOCs reduces test cost. ATWs enable analog test using digital, test access mechanisms, thereby reducing the need for expensive mixed-signal testers. However, analog cores, which tend to be application-specific, evolve more than digital cores with changes in technology. The ATW specifications are therefore subject to change due to the speed/frequency requirements of the newer and faster analog cores that are embedded in the SOC. These changes in specifications require the redesign of the data converters in an ATW. We propose an automated parameter translation and ATW redesign methodology. We demonstrate the effectiveness of our methodology using a set of analog tests specified for a representative analog core. We further study the tradeoffs between test time and silicon area. Experimental results are presented for three TTC'02 benchmark SOCs that have been augmented with five representative, analog cores.
AB - The manufacturing test cost for mixed-signal SOCs is widely recognized to be much higher than that for digital SOCs. It has been shown in recent prior work that the use of analog test wrappers (ATWs) for embedded analog cores in mixed-signal. SOCs reduces test cost. ATWs enable analog test using digital, test access mechanisms, thereby reducing the need for expensive mixed-signal testers. However, analog cores, which tend to be application-specific, evolve more than digital cores with changes in technology. The ATW specifications are therefore subject to change due to the speed/frequency requirements of the newer and faster analog cores that are embedded in the SOC. These changes in specifications require the redesign of the data converters in an ATW. We propose an automated parameter translation and ATW redesign methodology. We demonstrate the effectiveness of our methodology using a set of analog tests specified for a representative analog core. We further study the tradeoffs between test time and silicon area. Experimental results are presented for three TTC'02 benchmark SOCs that have been augmented with five representative, analog cores.
UR - http://www.scopus.com/inward/record.url?scp=33748568135&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33748568135&partnerID=8YFLogxK
U2 - 10.1109/ICCD.2005.8
DO - 10.1109/ICCD.2005.8
M3 - Conference contribution
AN - SCOPUS:33748568135
SN - 0769524516
SN - 9780769524511
T3 - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
SP - 137
EP - 142
BT - Proceedings - 2005 IEEE International Conference on Computer Design
T2 - 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005
Y2 - 2 October 2005 through 5 October 2005
ER -