A flexible design methodology for analog test wrappers in mixed-signal SOCs

Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

The manufacturing test cost for mixed-signal SOCs is widely recognized to be much higher than that for digital SOCs. It has been shown in recent prior work that the use of analog test wrappers (ATWs) for embedded analog cores in mixed-signal. SOCs reduces test cost. ATWs enable analog test using digital, test access mechanisms, thereby reducing the need for expensive mixed-signal testers. However, analog cores, which tend to be application-specific, evolve more than digital cores with changes in technology. The ATW specifications are therefore subject to change due to the speed/frequency requirements of the newer and faster analog cores that are embedded in the SOC. These changes in specifications require the redesign of the data converters in an ATW. We propose an automated parameter translation and ATW redesign methodology. We demonstrate the effectiveness of our methodology using a set of analog tests specified for a representative analog core. We further study the tradeoffs between test time and silicon area. Experimental results are presented for three TTC'02 benchmark SOCs that have been augmented with five representative, analog cores.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Pages137-142
Number of pages6
Volume2005
DOIs
StatePublished - 2005
Externally publishedYes
Event2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005 - San Jose, CA, United States
Duration: Oct 2 2005Oct 5 2005

Other

Other2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005
CountryUnited States
CitySan Jose, CA
Period10/2/0510/5/05

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture

Cite this

Sehgal, A., Ozev, S., & Chakrabarty, K. (2005). A flexible design methodology for analog test wrappers in mixed-signal SOCs. In Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors (Vol. 2005, pp. 137-142). [1524143] https://doi.org/10.1109/ICCD.2005.8

A flexible design methodology for analog test wrappers in mixed-signal SOCs. / Sehgal, Anuja; Ozev, Sule; Chakrabarty, Krishnendu.

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Vol. 2005 2005. p. 137-142 1524143.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sehgal, A, Ozev, S & Chakrabarty, K 2005, A flexible design methodology for analog test wrappers in mixed-signal SOCs. in Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. vol. 2005, 1524143, pp. 137-142, 2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005, San Jose, CA, United States, 10/2/05. https://doi.org/10.1109/ICCD.2005.8
Sehgal A, Ozev S, Chakrabarty K. A flexible design methodology for analog test wrappers in mixed-signal SOCs. In Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Vol. 2005. 2005. p. 137-142. 1524143 https://doi.org/10.1109/ICCD.2005.8
Sehgal, Anuja ; Ozev, Sule ; Chakrabarty, Krishnendu. / A flexible design methodology for analog test wrappers in mixed-signal SOCs. Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors. Vol. 2005 2005. pp. 137-142
@inproceedings{0633d98c615742d48b8cc6fbf02cca8c,
title = "A flexible design methodology for analog test wrappers in mixed-signal SOCs",
abstract = "The manufacturing test cost for mixed-signal SOCs is widely recognized to be much higher than that for digital SOCs. It has been shown in recent prior work that the use of analog test wrappers (ATWs) for embedded analog cores in mixed-signal. SOCs reduces test cost. ATWs enable analog test using digital, test access mechanisms, thereby reducing the need for expensive mixed-signal testers. However, analog cores, which tend to be application-specific, evolve more than digital cores with changes in technology. The ATW specifications are therefore subject to change due to the speed/frequency requirements of the newer and faster analog cores that are embedded in the SOC. These changes in specifications require the redesign of the data converters in an ATW. We propose an automated parameter translation and ATW redesign methodology. We demonstrate the effectiveness of our methodology using a set of analog tests specified for a representative analog core. We further study the tradeoffs between test time and silicon area. Experimental results are presented for three TTC'02 benchmark SOCs that have been augmented with five representative, analog cores.",
author = "Anuja Sehgal and Sule Ozev and Krishnendu Chakrabarty",
year = "2005",
doi = "10.1109/ICCD.2005.8",
language = "English (US)",
isbn = "0769524516",
volume = "2005",
pages = "137--142",
booktitle = "Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors",

}

TY - GEN

T1 - A flexible design methodology for analog test wrappers in mixed-signal SOCs

AU - Sehgal, Anuja

AU - Ozev, Sule

AU - Chakrabarty, Krishnendu

PY - 2005

Y1 - 2005

N2 - The manufacturing test cost for mixed-signal SOCs is widely recognized to be much higher than that for digital SOCs. It has been shown in recent prior work that the use of analog test wrappers (ATWs) for embedded analog cores in mixed-signal. SOCs reduces test cost. ATWs enable analog test using digital, test access mechanisms, thereby reducing the need for expensive mixed-signal testers. However, analog cores, which tend to be application-specific, evolve more than digital cores with changes in technology. The ATW specifications are therefore subject to change due to the speed/frequency requirements of the newer and faster analog cores that are embedded in the SOC. These changes in specifications require the redesign of the data converters in an ATW. We propose an automated parameter translation and ATW redesign methodology. We demonstrate the effectiveness of our methodology using a set of analog tests specified for a representative analog core. We further study the tradeoffs between test time and silicon area. Experimental results are presented for three TTC'02 benchmark SOCs that have been augmented with five representative, analog cores.

AB - The manufacturing test cost for mixed-signal SOCs is widely recognized to be much higher than that for digital SOCs. It has been shown in recent prior work that the use of analog test wrappers (ATWs) for embedded analog cores in mixed-signal. SOCs reduces test cost. ATWs enable analog test using digital, test access mechanisms, thereby reducing the need for expensive mixed-signal testers. However, analog cores, which tend to be application-specific, evolve more than digital cores with changes in technology. The ATW specifications are therefore subject to change due to the speed/frequency requirements of the newer and faster analog cores that are embedded in the SOC. These changes in specifications require the redesign of the data converters in an ATW. We propose an automated parameter translation and ATW redesign methodology. We demonstrate the effectiveness of our methodology using a set of analog tests specified for a representative analog core. We further study the tradeoffs between test time and silicon area. Experimental results are presented for three TTC'02 benchmark SOCs that have been augmented with five representative, analog cores.

UR - http://www.scopus.com/inward/record.url?scp=33748568135&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33748568135&partnerID=8YFLogxK

U2 - 10.1109/ICCD.2005.8

DO - 10.1109/ICCD.2005.8

M3 - Conference contribution

SN - 0769524516

SN - 9780769524511

VL - 2005

SP - 137

EP - 142

BT - Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

ER -