A dual mode redundant approach for microprocessor soft error hardness

Lawrence T. Clark; Dan W. Patterson; Nathan D. Hindman; Keith Holbert; Satendra Maurya; Steven M. Guertin

doi:10.1109/TNS.2011.2168828

A dual mode redundant approach for microprocessor soft error hardness

Lawrence T. Clark, Dan W. Patterson, Nathan D. Hindman, Keith Holbert, Satendra Maurya, Steven M. Guertin

Research output: Contribution to journal › Article › peer-review

16 Scopus citations

Abstract

A dual mode redundant (DMR) logic data path with instruction restart that detects errors at register file (RF) write-back is presented. The DMR RF allows SEU correction using parity to detect RF entry nibbles that are correct in one copy but not the other. Detection and backing out incorrect write data are also described. The radiation hardened by design (RHBD) circuits are implemented in 90 nm CMOS. The DMR microarchitecture is described, including pipelining, error handling, and the associated hardware. Heavy ion and proton testing validate the approach. Experimentally measured cross sections and examples of errors due to pipeline SET or RF SEU are shown. Critical node spacing and the mitigation of multiple node collection are also described.

Original language	English (US)
Article number	6084712
Pages (from-to)	3018-3025
Number of pages	8
Journal	IEEE Transactions on Nuclear Science
Volume	58
Issue number	6 PART 1
DOIs	https://doi.org/10.1109/TNS.2011.2168828
State	Published - Dec 2011

Keywords

Dual mode redundancy
error correction
radiation hardening
register files
sequential logic circuits
single event effects
soft errors
total ionizing dose

ASJC Scopus subject areas

Nuclear and High Energy Physics
Nuclear Energy and Engineering
Electrical and Electronic Engineering

Access to Document

10.1109/TNS.2011.2168828

Cite this

@article{2a70dbee187e496dbf10ed328c99e7a4,

title = "A dual mode redundant approach for microprocessor soft error hardness",

abstract = "A dual mode redundant (DMR) logic data path with instruction restart that detects errors at register file (RF) write-back is presented. The DMR RF allows SEU correction using parity to detect RF entry nibbles that are correct in one copy but not the other. Detection and backing out incorrect write data are also described. The radiation hardened by design (RHBD) circuits are implemented in 90 nm CMOS. The DMR microarchitecture is described, including pipelining, error handling, and the associated hardware. Heavy ion and proton testing validate the approach. Experimentally measured cross sections and examples of errors due to pipeline SET or RF SEU are shown. Critical node spacing and the mitigation of multiple node collection are also described.",

keywords = "Dual mode redundancy, error correction, radiation hardening, register files, sequential logic circuits, single event effects, soft errors, total ionizing dose",

author = "Clark, {Lawrence T.} and Patterson, {Dan W.} and Hindman, {Nathan D.} and Keith Holbert and Satendra Maurya and Guertin, {Steven M.}",

note = "Funding Information: Manuscript received July 22, 2011; revised September 10, 2011; accepted September 11, 2011. Date of publication November 18, 2011; date of current version December 14, 2011. This work was supported by the U.S. Air Force Research Labs in Albuquerque, NM. S. Guertin{\textquoteright}s research was carried out at the Jet Propulsion Laboratory, California Institute of Technology, under a contract with the National Aeronautics and Space Administration and supported through the Director{\textquoteright}s Research and Development Fund.",

year = "2011",

month = dec,

doi = "10.1109/TNS.2011.2168828",

language = "English (US)",

volume = "58",

pages = "3018--3025",

journal = "IEEE Transactions on Nuclear Science",

issn = "0018-9499",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "6 PART 1",

}

TY - JOUR

T1 - A dual mode redundant approach for microprocessor soft error hardness

AU - Clark, Lawrence T.

AU - Patterson, Dan W.

AU - Hindman, Nathan D.

AU - Holbert, Keith

AU - Maurya, Satendra

AU - Guertin, Steven M.

N1 - Funding Information: Manuscript received July 22, 2011; revised September 10, 2011; accepted September 11, 2011. Date of publication November 18, 2011; date of current version December 14, 2011. This work was supported by the U.S. Air Force Research Labs in Albuquerque, NM. S. Guertin’s research was carried out at the Jet Propulsion Laboratory, California Institute of Technology, under a contract with the National Aeronautics and Space Administration and supported through the Director’s Research and Development Fund.

PY - 2011/12

Y1 - 2011/12

N2 - A dual mode redundant (DMR) logic data path with instruction restart that detects errors at register file (RF) write-back is presented. The DMR RF allows SEU correction using parity to detect RF entry nibbles that are correct in one copy but not the other. Detection and backing out incorrect write data are also described. The radiation hardened by design (RHBD) circuits are implemented in 90 nm CMOS. The DMR microarchitecture is described, including pipelining, error handling, and the associated hardware. Heavy ion and proton testing validate the approach. Experimentally measured cross sections and examples of errors due to pipeline SET or RF SEU are shown. Critical node spacing and the mitigation of multiple node collection are also described.

AB - A dual mode redundant (DMR) logic data path with instruction restart that detects errors at register file (RF) write-back is presented. The DMR RF allows SEU correction using parity to detect RF entry nibbles that are correct in one copy but not the other. Detection and backing out incorrect write data are also described. The radiation hardened by design (RHBD) circuits are implemented in 90 nm CMOS. The DMR microarchitecture is described, including pipelining, error handling, and the associated hardware. Heavy ion and proton testing validate the approach. Experimentally measured cross sections and examples of errors due to pipeline SET or RF SEU are shown. Critical node spacing and the mitigation of multiple node collection are also described.

KW - Dual mode redundancy

KW - error correction

KW - radiation hardening

KW - register files

KW - sequential logic circuits

KW - single event effects

KW - soft errors

KW - total ionizing dose

UR - http://www.scopus.com/inward/record.url?scp=83855162254&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=83855162254&partnerID=8YFLogxK

U2 - 10.1109/TNS.2011.2168828

DO - 10.1109/TNS.2011.2168828

M3 - Article

AN - SCOPUS:83855162254

SN - 0018-9499

VL - 58

SP - 3018

EP - 3025

JO - IEEE Transactions on Nuclear Science

JF - IEEE Transactions on Nuclear Science

IS - 6 PART 1

M1 - 6084712

ER -

A dual mode redundant approach for microprocessor soft error hardness

Abstract

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this