A clock boosting scheme for low voltage circuits

Amir Ehsan Behradfar, Saeed Zeinolabedinzadeh, Khosrow HajSadeghi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Limitations in operation of analog switches at very low voltages have caused many problems in design of these types of switched capacitor circuits and data converters. In this paper by modifying a recently proposed clock boosting circuit, we could obtain a new structure with better performance for very low voltage circuits. This method requires simpler digital circuits in comparison with previously reported structures, as well as less number of transistors and smaller chip area. This method can be used for sampling the full swing signals with supply voltages as low as 0.4 volt.

Original languageEnglish (US)
Title of host publicationProceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
Pages21-24
Number of pages4
DOIs
StatePublished - Dec 26 2008
Externally publishedYes
Event15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 - St. Julian's, Malta
Duration: Aug 31 2008Sep 3 2008

Publication series

NameProceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

Conference

Conference15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
CountryMalta
CitySt. Julian's
Period8/31/089/3/08

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Behradfar, A. E., Zeinolabedinzadeh, S., & HajSadeghi, K. (2008). A clock boosting scheme for low voltage circuits. In Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 (pp. 21-24). [4674781] (Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008). https://doi.org/10.1109/ICECS.2008.4674781