Abstract

Ring oscillators (ROs) provide a low-cost digital VCO solution in fully integrated PLLs. However, due to their supply noise sensitivity and high noise floor, their applications have been limited to low-performance applications. The proposed architecture introduces an analog feed-forward adaptive phase-noise cancellation architecture that extracts and suppresses phase noise of ROs outside the PLL bandwidth. The proposed technique can improve the phase noise at an arbitrary offset frequency and bandwidth, and, after initial calibration for gain, it is insensitive to process, voltage, and temperature variations. An experimental fractional PLL, with a loop bandwidth of 200 kHz, is utilized to demonstrate the active phase-noise cancellation approach. The cancellation loop is designed to suppress the phase noise at 1-MHz offset by 12.5 dB and reference spur by 13 dB with less than 17% increase in the overall power consumption at 5.1-GHz frequency. The measured phase noise at 1-MHz offset after cancellation is-105 dBc/Hz. The proposed RO-PLL is fabricated in 90-nm CMOS process. With noise cancellation loop enabled, the PLL consumes 24.7 mA at 1.2-V supply.

Original languageEnglish (US)
Article number6490428
Pages (from-to)1151-1160
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Volume48
Issue number5
DOIs
StatePublished - 2013

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Discriminators
Phase noise
Phase locked loops
Bandwidth
Variable frequency oscillators
Electric power utilization
Calibration
Electric potential
Costs

Keywords

  • Delay-discriminator
  • frequency synthesizer
  • phase-locked loop (PLL)
  • ring-oscillator VCO

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

A 90-nm CMOS 5-GHz ring-oscillator pll with delay-discriminator-based active phase-noise cancellation. / Min, Seungkee; Copani, Tino; Kiaei, Sayfe; Bakkaloglu, Bertan.

In: IEEE Journal of Solid-State Circuits, Vol. 48, No. 5, 6490428, 2013, p. 1151-1160.

Research output: Contribution to journalArticle

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abstract = "Ring oscillators (ROs) provide a low-cost digital VCO solution in fully integrated PLLs. However, due to their supply noise sensitivity and high noise floor, their applications have been limited to low-performance applications. The proposed architecture introduces an analog feed-forward adaptive phase-noise cancellation architecture that extracts and suppresses phase noise of ROs outside the PLL bandwidth. The proposed technique can improve the phase noise at an arbitrary offset frequency and bandwidth, and, after initial calibration for gain, it is insensitive to process, voltage, and temperature variations. An experimental fractional PLL, with a loop bandwidth of 200 kHz, is utilized to demonstrate the active phase-noise cancellation approach. The cancellation loop is designed to suppress the phase noise at 1-MHz offset by 12.5 dB and reference spur by 13 dB with less than 17{\%} increase in the overall power consumption at 5.1-GHz frequency. The measured phase noise at 1-MHz offset after cancellation is-105 dBc/Hz. The proposed RO-PLL is fabricated in 90-nm CMOS process. With noise cancellation loop enabled, the PLL consumes 24.7 mA at 1.2-V supply.",
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