A 90 nm bulk CMOS radiation hardened by design cache memory

Xiaoyin Yao, Lawrence T. Clark, Dan W. Patterson, Keith Holbert

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A RHBD high performance cache fabricated on 90 nm bulk CMOS is presented. Test silicon cache data arrays can read and write at 1.02 GHz. Irradiation to 2 Mrad(Si) negligibly impacts standby current. The cache is write-through, and relies on error checking to allow cache invalidation when single event upsets or potential single event transients are detected. The write-through cache architectural state will then naturally be reloaded by the ensuing microprocessor operations. Single cycle invalidation is supported. Single event error ion beam test results are presented, as is a description of measured single event effects in array and peripheral circuits and their mitigation by the design.

Original languageEnglish (US)
Title of host publicationProceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS
Pages473-480
Number of pages8
DOIs
StatePublished - 2009
Event2009 10th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2009 - Bruges, Belgium
Duration: Sep 14 2009Sep 18 2009

Other

Other2009 10th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2009
CountryBelgium
CityBruges
Period9/14/099/18/09

Fingerprint

Cache memory
CMOS
Radiation
radiation
Ion beams
single event upsets
Microprocessor chips
microprocessors
Irradiation
Silicon
Networks (circuits)
ion beams
cycles
irradiation
silicon

Keywords

  • CMOS memory integrated circuits
  • heavy ion beams
  • high-speed integrated circuits
  • Radiation hardening

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Radiation

Cite this

Yao, X., Clark, L. T., Patterson, D. W., & Holbert, K. (2009). A 90 nm bulk CMOS radiation hardened by design cache memory. In Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS (pp. 473-480). [5994698] https://doi.org/10.1109/RADECS.2009.5994698

A 90 nm bulk CMOS radiation hardened by design cache memory. / Yao, Xiaoyin; Clark, Lawrence T.; Patterson, Dan W.; Holbert, Keith.

Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS. 2009. p. 473-480 5994698.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yao, X, Clark, LT, Patterson, DW & Holbert, K 2009, A 90 nm bulk CMOS radiation hardened by design cache memory. in Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS., 5994698, pp. 473-480, 2009 10th European Conference on Radiation and Its Effects on Components and Systems, RADECS 2009, Bruges, Belgium, 9/14/09. https://doi.org/10.1109/RADECS.2009.5994698
Yao X, Clark LT, Patterson DW, Holbert K. A 90 nm bulk CMOS radiation hardened by design cache memory. In Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS. 2009. p. 473-480. 5994698 https://doi.org/10.1109/RADECS.2009.5994698
Yao, Xiaoyin ; Clark, Lawrence T. ; Patterson, Dan W. ; Holbert, Keith. / A 90 nm bulk CMOS radiation hardened by design cache memory. Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS. 2009. pp. 473-480
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