24.5 A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning

Xin Si, Jia Jing Chen, Yung Ning Tu, Wei Hsing Huang, Jing Hong Wang, Yen Cheng Chiu, Wei Chen Wei, Ssu Yen Wu, Xiaoyu Sun, Rui Liu, Shimeng Yu, Ren Shuo Liu, Chih Cheng Hsieh, Kea Tiong Tang, Qiang Li, Meng Fan Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

45 Scopus citations

Abstract

Computation-in-memory (CIM) is a promising avenue to improve the energy efficiency of multiply-and-accumulate (MAC) operations in AI chips. Multi-bit CNNs are required for high-inference accuracy in many applications [1-5]. There are challenges and tradeoffs for SRAM-based CIM: (1) tradeoffs between signal margin, cell stability and area overhead; (2) the high-weighted bit process variation dominates the end-result error rate; (3) trade-off between input bandwidth, speed and area. Previous SRAM CIM macros were limited to binary MAC operations for fully connected networks [1], or they used CIM for multiplication [2] or weight-combination operations [3] with additional large-area near-memory computing (NMC) logic for summation or MAC operations.

Original languageEnglish (US)
Title of host publication2019 IEEE International Solid-State Circuits Conference, ISSCC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages396-398
Number of pages3
ISBN (Electronic)9781538685310
DOIs
StatePublished - Mar 6 2019
Event2019 IEEE International Solid-State Circuits Conference, ISSCC 2019 - San Francisco, United States
Duration: Feb 17 2019Feb 21 2019

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume2019-February
ISSN (Print)0193-6530

Conference

Conference2019 IEEE International Solid-State Circuits Conference, ISSCC 2019
CountryUnited States
CitySan Francisco
Period2/17/192/21/19

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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