24.5 A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning

Xin Si; Jia Jing Chen; Yung Ning Tu; Wei Hsing Huang; Jing Hong Wang; Yen Cheng Chiu; Wei Chen Wei; Ssu Yen Wu; Xiaoyu Sun; Rui Liu; Shimeng Yu; Ren Shuo Liu; Chih Cheng Hsieh; Kea Tiong Tang; Qiang Li; Meng Fan Chang

doi:10.1109/ISSCC.2019.8662392

24.5 A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning

Xin Si, Jia Jing Chen, Yung Ning Tu, Wei Hsing Huang, Jing Hong Wang, Yen Cheng Chiu, Wei Chen Wei, Ssu Yen Wu, Xiaoyu Sun, Rui Liu, Shimeng Yu, Ren Shuo Liu, Chih Cheng Hsieh, Kea Tiong Tang, Qiang Li, Meng Fan Chang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

192 Scopus citations

Abstract

Computation-in-memory (CIM) is a promising avenue to improve the energy efficiency of multiply-and-accumulate (MAC) operations in AI chips. Multi-bit CNNs are required for high-inference accuracy in many applications [1-5]. There are challenges and tradeoffs for SRAM-based CIM: (1) tradeoffs between signal margin, cell stability and area overhead; (2) the high-weighted bit process variation dominates the end-result error rate; (3) trade-off between input bandwidth, speed and area. Previous SRAM CIM macros were limited to binary MAC operations for fully connected networks [1], or they used CIM for multiplication [2] or weight-combination operations [3] with additional large-area near-memory computing (NMC) logic for summation or MAC operations.

Original language	English (US)
Title of host publication	2019 IEEE International Solid-State Circuits Conference, ISSCC 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	396-398
Number of pages	3
ISBN (Electronic)	9781538685310
DOIs	https://doi.org/10.1109/ISSCC.2019.8662392
State	Published - Mar 6 2019
Event	2019 IEEE International Solid-State Circuits Conference, ISSCC 2019 - San Francisco, United States Duration: Feb 17 2019 → Feb 21 2019

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	2019-February
ISSN (Print)	0193-6530

Conference

Conference	2019 IEEE International Solid-State Circuits Conference, ISSCC 2019
Country/Territory	United States
City	San Francisco
Period	2/17/19 → 2/21/19

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/ISSCC.2019.8662392

Cite this

Si, X., Chen, J. J., Tu, Y. N., Huang, W. H., Wang, J. H., Chiu, Y. C., Wei, W. C., Wu, S. Y., Sun, X., Liu, R., Yu, S., Liu, R. S., Hsieh, C. C., Tang, K. T., Li, Q., & Chang, M. F. (2019). 24.5 A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning. In 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019 (pp. 396-398). Article 8662392 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 2019-February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2019.8662392

24.5 A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning. / Si, Xin; Chen, Jia Jing; Tu, Yung Ning et al.
2019 IEEE International Solid-State Circuits Conference, ISSCC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. p. 396-398 8662392 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 2019-February).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Si, X, Chen, JJ, Tu, YN, Huang, WH, Wang, JH, Chiu, YC, Wei, WC, Wu, SY, Sun, X, Liu, R, Yu, S, Liu, RS, Hsieh, CC, Tang, KT, Li, Q & Chang, MF 2019, 24.5 A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning. in 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019., 8662392, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 2019-February, Institute of Electrical and Electronics Engineers Inc., pp. 396-398, 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019, San Francisco, United States, 2/17/19. https://doi.org/10.1109/ISSCC.2019.8662392

Si X, Chen JJ, Tu YN, Huang WH, Wang JH, Chiu YC et al. 24.5 A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning. In 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019. Institute of Electrical and Electronics Engineers Inc. 2019. p. 396-398. 8662392. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC.2019.8662392

@inproceedings{315e368fdd1d4d6baa4e0f4f79ba6d1e,

title = "24.5 A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning",

abstract = "Computation-in-memory (CIM) is a promising avenue to improve the energy efficiency of multiply-and-accumulate (MAC) operations in AI chips. Multi-bit CNNs are required for high-inference accuracy in many applications [1-5]. There are challenges and tradeoffs for SRAM-based CIM: (1) tradeoffs between signal margin, cell stability and area overhead; (2) the high-weighted bit process variation dominates the end-result error rate; (3) trade-off between input bandwidth, speed and area. Previous SRAM CIM macros were limited to binary MAC operations for fully connected networks [1], or they used CIM for multiplication [2] or weight-combination operations [3] with additional large-area near-memory computing (NMC) logic for summation or MAC operations.",

author = "Xin Si and Chen, {Jia Jing} and Tu, {Yung Ning} and Huang, {Wei Hsing} and Wang, {Jing Hong} and Chiu, {Yen Cheng} and Wei, {Wei Chen} and Wu, {Ssu Yen} and Xiaoyu Sun and Rui Liu and Shimeng Yu and Liu, {Ren Shuo} and Hsieh, {Chih Cheng} and Tang, {Kea Tiong} and Qiang Li and Chang, {Meng Fan}",

note = "Funding Information: The authors would like to thank MOST-Taiwan, CIC, NTHU-TSMC JDP, NTHU-MTK-JDP, M31 for financial and manufacturing support. Funding Information: The authors would like to thank MOST-Taiwan, CIC, NTHU-TSMC JDP, NTHUMTK- JDP, M31 for financial and manufacturing support. Publisher Copyright: {\textcopyright} 2019 IEEE.; 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019 ; Conference date: 17-02-2019 Through 21-02-2019",

year = "2019",

month = mar,

day = "6",

doi = "10.1109/ISSCC.2019.8662392",

language = "English (US)",

series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "396--398",

booktitle = "2019 IEEE International Solid-State Circuits Conference, ISSCC 2019",

}

TY - GEN

T1 - 24.5 A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning

AU - Si, Xin

AU - Chen, Jia Jing

AU - Tu, Yung Ning

AU - Huang, Wei Hsing

AU - Wang, Jing Hong

AU - Chiu, Yen Cheng

AU - Wei, Wei Chen

AU - Wu, Ssu Yen

AU - Sun, Xiaoyu

AU - Liu, Rui

AU - Yu, Shimeng

AU - Liu, Ren Shuo

AU - Hsieh, Chih Cheng

AU - Tang, Kea Tiong

AU - Li, Qiang

AU - Chang, Meng Fan

N1 - Funding Information: The authors would like to thank MOST-Taiwan, CIC, NTHU-TSMC JDP, NTHU-MTK-JDP, M31 for financial and manufacturing support. Funding Information: The authors would like to thank MOST-Taiwan, CIC, NTHU-TSMC JDP, NTHUMTK- JDP, M31 for financial and manufacturing support. Publisher Copyright: © 2019 IEEE.

PY - 2019/3/6

Y1 - 2019/3/6

N2 - Computation-in-memory (CIM) is a promising avenue to improve the energy efficiency of multiply-and-accumulate (MAC) operations in AI chips. Multi-bit CNNs are required for high-inference accuracy in many applications [1-5]. There are challenges and tradeoffs for SRAM-based CIM: (1) tradeoffs between signal margin, cell stability and area overhead; (2) the high-weighted bit process variation dominates the end-result error rate; (3) trade-off between input bandwidth, speed and area. Previous SRAM CIM macros were limited to binary MAC operations for fully connected networks [1], or they used CIM for multiplication [2] or weight-combination operations [3] with additional large-area near-memory computing (NMC) logic for summation or MAC operations.

AB - Computation-in-memory (CIM) is a promising avenue to improve the energy efficiency of multiply-and-accumulate (MAC) operations in AI chips. Multi-bit CNNs are required for high-inference accuracy in many applications [1-5]. There are challenges and tradeoffs for SRAM-based CIM: (1) tradeoffs between signal margin, cell stability and area overhead; (2) the high-weighted bit process variation dominates the end-result error rate; (3) trade-off between input bandwidth, speed and area. Previous SRAM CIM macros were limited to binary MAC operations for fully connected networks [1], or they used CIM for multiplication [2] or weight-combination operations [3] with additional large-area near-memory computing (NMC) logic for summation or MAC operations.

UR - http://www.scopus.com/inward/record.url?scp=85063542939&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85063542939&partnerID=8YFLogxK

U2 - 10.1109/ISSCC.2019.8662392

DO - 10.1109/ISSCC.2019.8662392

M3 - Conference contribution

AN - SCOPUS:85063542939

T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

SP - 396

EP - 398

BT - 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019

Y2 - 17 February 2019 through 21 February 2019

ER -

24.5 A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning

Abstract

Publication series

Conference

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this