21 fJ/step OTA-Less, Mismatch-Tolerant Continuous-Time VCO-Based Band-Pass ADC

Sanjeev Tannirkulam Chandrasekaran, Stefano Pietri, Arindam Sanyal

Research output: Contribution to journalArticlepeer-review

Abstract

A continuous-time band-pass (BP) delta-sigma (DS) analog-to-digital converter (ADC) is presented in this letter. The proposed BP ADC has four time-interleaved (TI) sub-ADCs that use ring oscillators as phase-domain integrators to achieve second-order noise shaping. The proposed BP-ADC architecture ensures that spurious tones due to mismatch between sub-ADCs fall out of the signal band and also have intrinsic interferer rejection capability. A prototype ADC fabricated in 65-nm CMOS is operated at an IF of 52 MHz. The ADC has SNDR of 63.1 and 59.5 dB at 1.04 and 4.3-MHz bandwidth, respectively. The ADC consumes only 0.36-mW power from a 0.9-V supply and has an energy efficiency of 21 fJ/step improving upon the current state of the art by 3.5×.

Original languageEnglish (US)
Article number9178737
Pages (from-to)342-345
Number of pages4
JournalIEEE Solid-State Circuits Letters
Volume3
DOIs
StatePublished - 2020
Externally publishedYes

Keywords

  • Analog-to-digital converter (ADC)
  • band-pass (BP) delta-sigma (DS)
  • time interleaved (TI)
  • voltage-controlled oscillator (VCO)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of '21 fJ/step OTA-Less, Mismatch-Tolerant Continuous-Time VCO-Based Band-Pass ADC'. Together they form a unique fingerprint.

Cite this