Statement of Work for Arizona State University Ultimate Switches (US) Srabanti Chowdhury and Robert Nemanich Application Control Number 0942-1513; ASU Proposal 14010058 The purpose of this project is to develop manufacturable 1200V single chip normally-off transistors which meet the performance and cost targets of SWITCHES. The approach is to investigate three novel promising devices and establish the feasibility of delivering high performance at low cost. Devices that do not show promise will not be pursued beyond 18 months. Both vertical devices on GaN substrates and inverted vertical transistors on Si substrates based on superjunction principles are presented. All transistors simultaneously minimize the chip area and Ron to reduce chip cost. DEVICE DESIGN AND FABRICATION i) Model transistors using two dimensional drift diffusion models (ASU). ii) Process development of etching (ASU, UCSB), implantation, activation (NR , ASU), and dielectrics: ALD (ASU). iii) Device fabrication of CAVETs (ASU), Vertical MOSFET (ASU, UCSB), vertical JFET (ASU).
|Effective start/end date||3/10/14 → 8/31/16|
- US Department of Energy (DOE): $642,725.00
Junction gate field effect transistors