Scaling of On-Chip Inductors Towards 50 um Size through Integration of Magnetic Materials

Project: Research project

Project Details

Description

Scaling of On-Chip Inductors Towards 50 um Size through Integration of Magnetic Materials Scaling of On-Chip Inductors Towards 50 um Size through Integration of Magnetic Materials SOW Scaling the size of inductors down to 50 m while satisfying all performance requirements, including 1 nH inductance at 5 GHz. Inductor scaling will be achieved by introducing magnetic materials with the optimum patterning and geometry to significantly improve ferromagnetic resonance frequency and to reduce eddy current losses. These efforts will produce inductors with much higher area efficiency and quality, enabling applications in radio frequency and analog/mixed signal circuit design, such as power amplifier, distributed wireless circuits, low noise amplifiers, high-speed signaling and clocking, which will benefit ultimately the efficient integration for System-on-Chip (SoC) and System-in-Package (SiP) applications. Highly scaled inductors will greatly reduce the size of passives for interconnect and packaging applications.
StatusFinished
Effective start/end date6/1/126/30/13

Funding

  • SRCCO Inc.: $96,745.00

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