In response to a technology concept request from a government agency, a proposal has been awarded to JPL to develop a highly efficient fully integrated rad-hard digitally controlled programmable point-of-load (POL) regulator that can reliably power application specific integrated circuits (ASICs) built with 45 nm technology. In this work, we are proposing to productize a design concept that was developed under NASA-JPL directors research and development funds [1-3]. As previously reported at venues such as NSREC and ISSCC 2011, this topology concept is well suited for space applications. The design is the first fully integrated digitally controlled programmable POL that uses a novel digital control scheme to mitigate single event effects. Two prototypes, a high and low voltage version, have been designed, fabricated and tested in a commercial foundry and has shown great performances [1-3]. The main characteristics of this design are: 1 to 5.5 V (or 12 V) input voltage, 1 - 4.5 V regulated output voltage, high efficiency (peak efficiency at 94%) and power up to 5W. The involvement of Arizona State University for this program is the transitioning of the existing design into a selected process with smaller feature sizes (likely 0.18 or 0.13 um technology) and the development of new features to productize this concept. Due to its fully integrated solution, the design will be very small with die area estimated at 1.2x1.2 mm2 and packaged in a 28 pins reliable co-fired ceramic (HTCC) carrier suitable for high reliability missions.
|Effective start/end date||9/27/12 → 11/30/14|
- National Aeronautics Space Administration (NASA): $276,000.00