The minimum feature size of CMOS technology is expected to reach 10nm in ten years. The grand challenge to the IC design community is to identify unconventional materials and structures and integrate them into the circuit architecture. This is especially true for future memory design, as traditional CMOS based SRAM design is tremendously challenged by shortchannel effects, process variability, and reliability degradation. Recently, several emerging memory technologies have been actively researched as alternatives post the silicon era, such as phase-change memory (PRAM), spin-transfer torque magnetic memory (STT-MRAM), resistive memory (RRAM), and ferromagnetic memory (FeRAM). These devices are diverse in their physical operation and performance. These devices are quite different and there is no winner-of-all for key performance metrics. To exploit the advantages of these devices, it is desirable to develop an innovative design methodology that is capable of conducting path-finding at the early stage, evaluate the tradeoffs among different choices, and integrate post-Si memory cells for optimal system performance. Similar as silicon based SRAM or DRAM design, heterogeneous memory design must start at the device level, in order to comprehend the underlying physical mechanisms. Such a design methodology should incorporate device-level models of various memory types, effectively bridging the technology reality and design impact. It should also incorporate process variability and reliability effects, supporting large-scale memory integration with sufficient yield. In this project, we target to accomplish the above methodology through the joint efforts of the understanding of memory devices, physical modeling of reliability and variability, novel error correction techniques, and predictive design strategies.
|Effective start/end date||9/1/12 → 8/31/16|
- National Science Foundation (NSF): $440,000.00
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