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Personal profile

Education/Academic qualification

PHD, University of Maryland-College Park

… → 1990

MS, University of Maryland-College Park

… → 1986

BT, Indian Institute of Technology Kharagpur

… → 1984

Fingerprint Dive into the research topics where Chaitali Chakrabarti is active. These topic labels come from the works of this person. Together they form a unique fingerprint.

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Research Output

A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm

Pal, S., Park, D. H., Feng, S., Gao, P., Tan, J., Rovinski, A., Xie, S., Zhao, C., Amarnath, A., Wesley, T., Beaumont, J., Chen, K. Y., Chakrabarti, C., Taylor, M., Mudge, T., Blaauw, D., Kim, H. S. & Dreslinski, R., Jun 2019, 2019 Symposium on VLSI Circuits, VLSI Circuits 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., p. C150-C151 8778147. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; vol. 2019-June).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm

    Pal, S., Park, D. H., Feng, S., Gao, P., Tan, J., Rovinski, A., Xie, S., Zhao, C., Amarnath, A., Wesley, T., Beaumont, J., Chen, K. Y., Chakrabarti, C., Taylor, M., Mudge, T., Blaauw, D., Kim, H. S. & Dreslinski, R., Jun 1 2019, 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., p. C150-C151 8776507. (Digest of Technical Papers - Symposium on VLSI Technology; vol. 2019-June).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • A 8.93-TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity with All Parameters Stored On-Chip

    Kadetotad, D., Berisha, V., Chakrabarti, C. & Seo, J. S., Sep 2019, ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., p. 119-122 4 p. 8902809. (ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • A Deep Q-Learning Approach for Dynamic Management of Heterogeneous Processors

    Gupta, U., Mandal, S. K., Mao, M., Chakrabarti, C. & Ogras, U., Jan 1 2019, (Accepted/In press) In : IEEE Computer Architecture Letters.

    Research output: Contribution to journalArticle

  • 6 Scopus citations
    Open Access
  • Projects