Abstract
Sorting network based architectures for computing nonre-cursive and recursive median filters are presented. The proposed architectures are highly pipelined and consist of fewer compare-swap units than existing architectures. The reduction in the number of compare-swap units is achieved by minimizing computational overlap between successive outputs and also by using Batcher's odd-even merge sort (instead of bubble-sort). The latency of these networks is reduced by building them with sorting units that sort 2 elements {sort-2) as well as 3 elements (sort-3) in 1 time unit.
Original language | English (US) |
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Pages (from-to) | 723-727 |
Number of pages | 5 |
Journal | IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing |
Volume | 40 |
Issue number | 11 |
DOIs | |
State | Published - Nov 1993 |
ASJC Scopus subject areas
- Signal Processing
- Electrical and Electronic Engineering