A Pipelined Associative Memory Implemented in VLSI

Lawrence T. Clark; Robert O. Grondin

doi:10.1109/4.16298

A Pipelined Associative Memory Implemented in VLSI

Lawrence T. Clark, Robert O. Grondin

Research output: Contribution to journal › Article › peer-review

7 Scopus citations

Abstract

A memory system which rapidly chooses the stored item most closely matching a given input is fundamental to a number of recognition tasks. The topic of this paper is a memory architecture which performs this function. In addition, a measure of the quality of the selected (best matching) memory is generated. The architecture is capable of significant data throughput rates, and is amenable to implementation using conventional digital VLSI fabrication processes. These characteristics are demonstrated by a prototype device fabricated using the MOSIS 3-(im CMOS design rules which can compare more than two million 9-bit input words per second. Behavioral simulations demonstrate the applicability of the architecture to some basic recognition tasks.

Original language	English (US)
Pages (from-to)	28-34
Number of pages	7
Journal	IEEE Journal of Solid-State Circuits
Volume	24
Issue number	1
DOIs	https://doi.org/10.1109/4.16298
State	Published - Feb 1989

ASJC Scopus subject areas

Electrical and Electronic Engineering

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note = "Funding Information: Manuscript received March 16, 1988; revised July 11, 1988. This work was supported by the Office of Naval Research under Award N00014-85-K-0387. The authors are with the Center for Solid State Electronics Research, Arizona State University, Tempe, AZ 85287. IEEE Log Number 8824927.",

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A Pipelined Associative Memory Implemented in VLSI

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