XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks

Shihui Yin, Zhewei Jiang, Jae Sun Seo, Mingoo Seok

Research output: Contribution to journalArticle

Abstract

We present XNOR-SRAM, a mixed-signal in-memory computing (IMC) SRAM macro that computes ternary-XNOR-and-accumulate (XAC) operations in binary/ternary deep neural networks (DNNs) without row-by-row data access. The XNOR-SRAM bitcell embeds circuits for ternary XNOR operations, which are accumulated on the read bitline (RBL) by simultaneously turning on all 256 rows, essentially forming a resistive voltage divider. The analog RBL voltage is digitized with a column-multiplexed 11-level flash analog-to-digital converter (ADC) at the XNOR-SRAM periphery. XNOR-SRAM is prototyped in a 65-nm CMOS and achieves the energy efficiency of 403 TOPS/W for ternary-XAC operations with 88.8% test accuracy for the CIFAR-10 data set at 0.6-V supply. This marks 33\times better energy efficiency and 300\times better energy-delay product than conventional digital hardware and also represents among the best tradeoff in energy efficiency and DNN accuracy.

Original languageEnglish (US)
Article number8959407
Pages (from-to)1733-1743
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume55
Issue number6
DOIs
StatePublished - Jun 2020

Keywords

  • Binary weights
  • SRAM
  • deep neural networks (DNNs)
  • ensemble learning
  • in-memory computing (IMC)
  • ternary activations

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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