XNOR-SRAM: In-memory computing SRAM macro for binary/ternary deep neural networks

Zhewei Jiang; Shihui Yin; Mingoo Seok; Jae-sun Seo

doi:10.1109/VLSIT.2018.8510687

XNOR-SRAM: In-memory computing SRAM macro for binary/ternary deep neural networks

Zhewei Jiang, Shihui Yin, Mingoo Seok, Jae-sun Seo

Arizona State University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

58 Scopus citations

Abstract

We present an in-memory computing SRAM macro that computes XNOR-and-accumulate in binary/ternary deep neural networks on the bitline without row-by-row data access. It achieves 33X better energy and 300X better energy-delay product than digital ASIC, and also achieves significantly higher accuracy than prior in-SRAM computing macro (e.g., 98.3% vs. 90% for MNIST) by being able to support the mainstream DNN/CNN algorithms.

Original language	English (US)
Title of host publication	2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	173-174
Number of pages	2
Volume	2018-June
ISBN (Electronic)	9781538642160
DOIs	https://doi.org/10.1109/VLSIT.2018.8510687
State	Published - Oct 25 2018
Event	38th IEEE Symposium on VLSI Technology, VLSI Technology 2018 - Honolulu, United States Duration: Jun 18 2018 → Jun 22 2018

Other

Other	38th IEEE Symposium on VLSI Technology, VLSI Technology 2018
Country	United States
City	Honolulu
Period	6/18/18 → 6/22/18

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/VLSIT.2018.8510687

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XNOR-SRAM : In-memory computing SRAM macro for binary/ternary deep neural networks. / Jiang, Zhewei; Yin, Shihui; Seok, Mingoo; Seo, Jae-sun.

2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018. Vol. 2018-June Institute of Electrical and Electronics Engineers Inc., 2018. p. 173-174 8510687.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Jiang, Z, Yin, S, Seok, M & Seo, J 2018, XNOR-SRAM: In-memory computing SRAM macro for binary/ternary deep neural networks. in 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018. vol. 2018-June, 8510687, Institute of Electrical and Electronics Engineers Inc., pp. 173-174, 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018, Honolulu, United States, 6/18/18. https://doi.org/10.1109/VLSIT.2018.8510687

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abstract = "We present an in-memory computing SRAM macro that computes XNOR-and-accumulate in binary/ternary deep neural networks on the bitline without row-by-row data access. It achieves 33X better energy and 300X better energy-delay product than digital ASIC, and also achieves significantly higher accuracy than prior in-SRAM computing macro (e.g., 98.3% vs. 90% for MNIST) by being able to support the mainstream DNN/CNN algorithms.",

author = "Zhewei Jiang and Shihui Yin and Mingoo Seok and Jae-sun Seo",

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XNOR-SRAM: In-memory computing SRAM macro for binary/ternary deep neural networks

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