Abstract
We present an in-memory computing SRAM macro that computes XNOR-and-accumulate in binary/ternary deep neural networks on the bitline without row-by-row data access. It achieves 33X better energy and 300X better energy-delay product than digital ASIC, and also achieves significantly higher accuracy than prior in-SRAM computing macro (e.g., 98.3% vs. 90% for MNIST) by being able to support the mainstream DNN/CNN algorithms.
| Original language | English (US) |
|---|---|
| Title of host publication | 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 173-174 |
| Number of pages | 2 |
| Volume | 2018-June |
| ISBN (Electronic) | 9781538642160 |
| DOIs | |
| State | Published - Oct 25 2018 |
| Event | 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018 - Honolulu, United States Duration: Jun 18 2018 → Jun 22 2018 |
Other
| Other | 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018 |
|---|---|
| Country | United States |
| City | Honolulu |
| Period | 6/18/18 → 6/22/18 |
Fingerprint
ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
XNOR-SRAM : In-memory computing SRAM macro for binary/ternary deep neural networks. / Jiang, Zhewei; Yin, Shihui; Seok, Mingoo; Seo, Jae-sun.
2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018. Vol. 2018-June Institute of Electrical and Electronics Engineers Inc., 2018. p. 173-174 8510687.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - XNOR-SRAM
T2 - In-memory computing SRAM macro for binary/ternary deep neural networks
AU - Jiang, Zhewei
AU - Yin, Shihui
AU - Seok, Mingoo
AU - Seo, Jae-sun
PY - 2018/10/25
Y1 - 2018/10/25
N2 - We present an in-memory computing SRAM macro that computes XNOR-and-accumulate in binary/ternary deep neural networks on the bitline without row-by-row data access. It achieves 33X better energy and 300X better energy-delay product than digital ASIC, and also achieves significantly higher accuracy than prior in-SRAM computing macro (e.g., 98.3% vs. 90% for MNIST) by being able to support the mainstream DNN/CNN algorithms.
AB - We present an in-memory computing SRAM macro that computes XNOR-and-accumulate in binary/ternary deep neural networks on the bitline without row-by-row data access. It achieves 33X better energy and 300X better energy-delay product than digital ASIC, and also achieves significantly higher accuracy than prior in-SRAM computing macro (e.g., 98.3% vs. 90% for MNIST) by being able to support the mainstream DNN/CNN algorithms.
UR - http://www.scopus.com/inward/record.url?scp=85056839915&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85056839915&partnerID=8YFLogxK
U2 - 10.1109/VLSIT.2018.8510687
DO - 10.1109/VLSIT.2018.8510687
M3 - Conference contribution
AN - SCOPUS:85056839915
VL - 2018-June
SP - 173
EP - 174
BT - 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018
PB - Institute of Electrical and Electronics Engineers Inc.
ER -