XNOR-SRAM: In-bitcell computing SRAM macro based on resistive computing mechanism

Zhewei Jiang, Shihui Yin, Jae Sun Seo, Mingoo Seok

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

We present an in-memory computing SRAM macro for binary neural networks. The memory macro computes XNOR-and-accumulate for binary/ternary deep convolutional neural networks on the bitline without row-by-row data access. It achieves 33X better energy and 300X better energy-delay-product than digital ASIC and achieves high accuracy in machine learning tasks (98.3% for MNIST and 85.7% for CIFAR-10 datasets).

Original languageEnglish (US)
Title of host publicationGLSVLSI 2019 - Proceedings of the 2019 Great Lakes Symposium on VLSI
PublisherAssociation for Computing Machinery
Pages417-422
Number of pages6
ISBN (Electronic)9781450362528
DOIs
StatePublished - May 13 2019
Event29th Great Lakes Symposium on VLSI, GLSVLSI 2019 - Tysons Corner, United States
Duration: May 9 2019May 11 2019

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Conference

Conference29th Great Lakes Symposium on VLSI, GLSVLSI 2019
Country/TerritoryUnited States
CityTysons Corner
Period5/9/195/11/19

Keywords

  • In-memory computing
  • Machine learning accelerator
  • Mixed-signal processing
  • Near-memory computing

ASJC Scopus subject areas

  • Engineering(all)

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