Xmas: Quick formal modeling of communication fabrics to enable verification

Satrajit Chatterjee, Michael Kishinevsky, Umit Y. Ogras

Research output: Contribution to journalArticlepeer-review

34 Scopus citations

Abstract

Although communication fabrics at the microarchitectural level are mainly composed of standard primitives such as queues and arbiters, to get an executable model one has to connect these primitives with glue logic to complete the description. In this paper we identify a richer set of microarchitectural primitives that allows us to describe complete systems by composition alone. This enables us to build models faster (since models are now simply wiring diagrams at an appropriate level of abstraction) and to avoid common modeling errors such as inadvertent loss of data due to incorrect timing assumptions. Our models are formal and they are used for model checking as well as dynamic validation and performance modeling. However, unlike other formalisms this approach leads to a precise yet intuitive graphical notation for microarchitecture that captures timing and functionality in sufficient detail to be useful for reasoning about correctness and for communicating microarchitectural ideas to RTL and circuit designers and validators.

Original languageEnglish (US)
Article number6225465
Pages (from-to)80-88
Number of pages9
JournalIEEE Design and Test of Computers
Volume29
Issue number3
DOIs
StatePublished - Oct 29 2012
Externally publishedYes

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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