TY - GEN
T1 - Workload-adaptive process tuning strategy for power- efficient multi-core processors
AU - Lee, Jungseob
AU - Wang, Chi Chao
AU - Ghasemi, Hamid
AU - Bircher, Lloyd
AU - Cao, Yu
AU - Kim, Nam Sung
PY - 2010
Y1 - 2010
N2 - As more devices are integrated with technology scaling, reducing the power consumption of both high-performance and low-power processors has become the first-class design constraint. Reducing power consumption while satisfying required performance is critical for increasing the operating time of mobile devices and lowering the operating cost of offices and data centers. Meanwhile, dynamic voltage and frequency scaling (DVFS) and clock-gating (CG) techniques have been widely used for two of the most powerful techniques to reduce the power consumption of such processors. Depending on performance and power demands, a processor runs at various performance and power states to trade power with performance. In this paper, we propose process tuning strategy to minimize the average power consumption of multi-core processors that use the DVFS and CG techniques, while providing the same maximum performance. The proposed optimization method incorporates with workload characteristics of commercial highperformance and low-power multi-core processors. The experimental results show that our optimized 32nm technologies for workstation, mobile, and server multi-core processors minimize the average power by up to 13, 18, and 9%, respectively.
AB - As more devices are integrated with technology scaling, reducing the power consumption of both high-performance and low-power processors has become the first-class design constraint. Reducing power consumption while satisfying required performance is critical for increasing the operating time of mobile devices and lowering the operating cost of offices and data centers. Meanwhile, dynamic voltage and frequency scaling (DVFS) and clock-gating (CG) techniques have been widely used for two of the most powerful techniques to reduce the power consumption of such processors. Depending on performance and power demands, a processor runs at various performance and power states to trade power with performance. In this paper, we propose process tuning strategy to minimize the average power consumption of multi-core processors that use the DVFS and CG techniques, while providing the same maximum performance. The proposed optimization method incorporates with workload characteristics of commercial highperformance and low-power multi-core processors. The experimental results show that our optimized 32nm technologies for workstation, mobile, and server multi-core processors minimize the average power by up to 13, 18, and 9%, respectively.
KW - DVFS
KW - Multi-core processor
KW - Process parameter tuning
UR - http://www.scopus.com/inward/record.url?scp=77957935379&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77957935379&partnerID=8YFLogxK
U2 - 10.1145/1840845.1840889
DO - 10.1145/1840845.1840889
M3 - Conference contribution
AN - SCOPUS:77957935379
SN - 9781450301466
T3 - Proceedings of the International Symposium on Low Power Electronics and Design
SP - 225
EP - 230
BT - ISLPED'10 - Proceedings of the 16th ACM/IEEE International Symposium on Low-Power Electronics and Design
T2 - 16th ACM/IEEE International Symposium on Low-Power Electronics and Design, ISLPED'10
Y2 - 18 August 2010 through 20 August 2010
ER -