Workload-adaptive process tuning strategy for power- efficient multi-core processors

Jungseob Lee, Chi Chao Wang, Hamid Ghasemi, Lloyd Bircher, Yu Cao, Nam Sung Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

As more devices are integrated with technology scaling, reducing the power consumption of both high-performance and low-power processors has become the first-class design constraint. Reducing power consumption while satisfying required performance is critical for increasing the operating time of mobile devices and lowering the operating cost of offices and data centers. Meanwhile, dynamic voltage and frequency scaling (DVFS) and clock-gating (CG) techniques have been widely used for two of the most powerful techniques to reduce the power consumption of such processors. Depending on performance and power demands, a processor runs at various performance and power states to trade power with performance. In this paper, we propose process tuning strategy to minimize the average power consumption of multi-core processors that use the DVFS and CG techniques, while providing the same maximum performance. The proposed optimization method incorporates with workload characteristics of commercial highperformance and low-power multi-core processors. The experimental results show that our optimized 32nm technologies for workstation, mobile, and server multi-core processors minimize the average power by up to 13, 18, and 9%, respectively.

Original languageEnglish (US)
Title of host publicationProceedings of the International Symposium on Low Power Electronics and Design
Pages225-230
Number of pages6
DOIs
StatePublished - 2010
Event16th ACM/IEEE International Symposium on Low-Power Electronics and Design, ISLPED'10 - Austin, TX, United States
Duration: Aug 18 2010Aug 20 2010

Other

Other16th ACM/IEEE International Symposium on Low-Power Electronics and Design, ISLPED'10
CountryUnited States
CityAustin, TX
Period8/18/108/20/10

Fingerprint

Electric power utilization
Tuning
Clocks
Computer workstations
Operating costs
Mobile devices
Servers
Voltage scaling
Dynamic frequency scaling

Keywords

  • DVFS
  • Multi-core processor
  • Process parameter tuning

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Lee, J., Wang, C. C., Ghasemi, H., Bircher, L., Cao, Y., & Kim, N. S. (2010). Workload-adaptive process tuning strategy for power- efficient multi-core processors. In Proceedings of the International Symposium on Low Power Electronics and Design (pp. 225-230) https://doi.org/10.1145/1840845.1840889

Workload-adaptive process tuning strategy for power- efficient multi-core processors. / Lee, Jungseob; Wang, Chi Chao; Ghasemi, Hamid; Bircher, Lloyd; Cao, Yu; Kim, Nam Sung.

Proceedings of the International Symposium on Low Power Electronics and Design. 2010. p. 225-230.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lee, J, Wang, CC, Ghasemi, H, Bircher, L, Cao, Y & Kim, NS 2010, Workload-adaptive process tuning strategy for power- efficient multi-core processors. in Proceedings of the International Symposium on Low Power Electronics and Design. pp. 225-230, 16th ACM/IEEE International Symposium on Low-Power Electronics and Design, ISLPED'10, Austin, TX, United States, 8/18/10. https://doi.org/10.1145/1840845.1840889
Lee J, Wang CC, Ghasemi H, Bircher L, Cao Y, Kim NS. Workload-adaptive process tuning strategy for power- efficient multi-core processors. In Proceedings of the International Symposium on Low Power Electronics and Design. 2010. p. 225-230 https://doi.org/10.1145/1840845.1840889
Lee, Jungseob ; Wang, Chi Chao ; Ghasemi, Hamid ; Bircher, Lloyd ; Cao, Yu ; Kim, Nam Sung. / Workload-adaptive process tuning strategy for power- efficient multi-core processors. Proceedings of the International Symposium on Low Power Electronics and Design. 2010. pp. 225-230
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